公开(公告)号：US20230307434A1

公开(公告)日：2023-09-28

申请号：US18203952

申请日：2023-05-31

申请人： Kioxia Corporation

发明人： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC分类号： H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

摘要： A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20220285284A1

公开(公告)日：2022-09-08

申请号：US17412022

申请日：2021-08-25

申请人： Kioxia Corporation

发明人： Yoichi MIZUTA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC分类号： H01L23/544 ,  H01L21/768 ,  H01L21/66

摘要： According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

公开(公告)号：US20230083158A1

公开(公告)日：2023-03-16

申请号：US17682889

申请日：2022-02-28

申请人： Kioxia Corporation

发明人： Kenichi MATOBA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Yoichi MIZUTA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC分类号： H01L27/11529 ,  H01L27/108

摘要： A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

公开(公告)号：US20220077128A1

公开(公告)日：2022-03-10

申请号：US17184837

申请日：2021-02-25

申请人： Kioxia Corporation

发明人： Akihiko CHIBA ,  Takahiro TSURUDO ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Hiroaki NAKASA ,  Hiroyuki TAKENAKA

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/528

摘要： A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

公开(公告)号：US20210118862A1

公开(公告)日：2021-04-22

申请号：US17012111

申请日：2020-09-04

申请人： Kioxia Corporation

发明人： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC分类号： H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

摘要： A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.