公开(公告)号：US20220285284A1

公开(公告)日：2022-09-08

申请号：US17412022

申请日：2021-08-25

申请人： Kioxia Corporation

发明人： Yoichi MIZUTA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC分类号： H01L23/544 ,  H01L21/768 ,  H01L21/66

摘要： According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

公开(公告)号：US20230083158A1

公开(公告)日：2023-03-16

申请号：US17682889

申请日：2022-02-28

申请人： Kioxia Corporation

发明人： Kenichi MATOBA ,  Takahiro TSURUDO ,  Yoshiaki TAKAHASHI ,  Yoichi MIZUTA ,  Yoshifumi SHIMAMURA ,  Toru OZAWA ,  Takumi KOSAKI ,  Kouji NAKAO

IPC分类号： H01L27/11529 ,  H01L27/108

摘要： A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

公开(公告)号：US20220077128A1

公开(公告)日：2022-03-10

申请号：US17184837

申请日：2021-02-25

申请人： Kioxia Corporation

发明人： Akihiko CHIBA ,  Takahiro TSURUDO ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Hiroaki NAKASA ,  Hiroyuki TAKENAKA

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/528

摘要： A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.