公开(公告)号：US20210407566A1

公开(公告)日：2021-12-30

申请号：US17187578

申请日：2021-02-26

Applicant: KIOXIA CORPORATION

Inventor： Yuuta SANO

IPC: G11C7/10

Abstract: A semiconductor storage device includes a memory cell array, and a peripheral circuit that is connected to the memory cell array, and that inputs and outputs user data in response to an input of a command set including command data and address data. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register column capable of storing n-bit data forming the command data. The address register includes an n-bit second register column capable of storing n-bit data forming the address data. The queue register includes a plurality of third register columns, each capable of storing at least (n+1) bit data, and each third register column is capable of storing the n-bit data forming the command data or the n-bit data forming the address data.

公开(公告)号：US20240306405A1

公开(公告)日：2024-09-12

申请号：US18590778

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Junichi SATO ,  Kazuto UEHARA ,  Yuuta SANO ,  Yoshihiro SAEKI

IPC: H10B80/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06582

Abstract: A semiconductor storage device comprises a memory chip including first and second control signal pads to which first and second control signals are to be input, respectively, a data signal pad to and from which a data signal is to be input and output, and a control circuit. The control circuit stores data in the data signal in a data register, when the first and second control signals are at a first state, stores data in the data signal in a command register, when the first control signal is at a second state and the second control signal is at the first state, stores data in the data signal in an address register, when the first control signal is at the first state and the second control signal is at the second state, and outputs status data when the first and second control signals are at the second state.