公开(公告)号：US20220310177A1

公开(公告)日：2022-09-29

申请号：US17470002

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Tomohiko ITO ,  Kazuto UEHARA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell and a first boosting circuit. The first boosting circuit generates a first voltage, a second voltage, and a third voltage lower than the second voltage at a first output terminal. The first, second and third voltages is used for a write operation. The write operation includes a first program operation and a first verify operation executed after the first program operation. The first boosting circuit generates the first voltage at the first output terminal during the first program operation, generates the third voltage at the first output terminal at end of the first program operation, generates the second voltage at the first output terminal during the first verify operation, and then generates the first voltage to the first output terminal during the first verify operation.

公开(公告)号：US20230317177A1

公开(公告)日：2023-10-05

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US20250046384A1

公开(公告)日：2025-02-06

申请号：US18923698

申请日：2024-10-23

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving a first command and an address indicating a region in the memory cell array, and a control circuit controlling a read operation to the memory cell array based on the first command. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US20240306405A1

公开(公告)日：2024-09-12

申请号：US18590778

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Junichi SATO ,  Kazuto UEHARA ,  Yuuta SANO ,  Yoshihiro SAEKI

IPC: H10B80/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06582

Abstract: A semiconductor storage device comprises a memory chip including first and second control signal pads to which first and second control signals are to be input, respectively, a data signal pad to and from which a data signal is to be input and output, and a control circuit. The control circuit stores data in the data signal in a data register, when the first and second control signals are at a first state, stores data in the data signal in a command register, when the first control signal is at a second state and the second control signal is at the first state, stores data in the data signal in an address register, when the first control signal is at the first state and the second control signal is at the second state, and outputs status data when the first and second control signals are at the second state.