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    Apparatus and method for electrical determination of delamination at one or more interfaces within a semiconductor wafer
    1.
    发明授权
    Apparatus and method for electrical determination of delamination at one or more interfaces within a semiconductor wafer 失效
    用于在半导体晶片内的一个或多个界面处电分离的电测定装置和方法

    公开(公告)号：US6066561A

    公开(公告)日：2000-05-23

    申请号：US995260

    申请日：1997-12-19

    申请人： Kiran Kumar ,  David J. Heine

    发明人： Kiran Kumar ,  David J. Heine

    IPC分类号： H01L21/66 ,  H01L21/00

    CPC分类号： H01L22/12

    摘要： An apparatus and method are presented for electrically determining whether delamination has occurred at one or more interfaces within a semiconductor wafer. The semiconductor wafer includes a test structure formed within dielectric layers upon an upper surface of a semiconductor substrate. The test structure includes an electrically conductive structure, a pair of electrically conductive contact plugs, and a probe pad. The conductive structure is formed within an opening in a first dielectric layer, and is in electrical contact with the upper surface of the semiconductor substrate. The conductive structure is preferably made up of the same vertical stack of layers of selected electrically conductive materials used to form interconnects within the semiconductor wafer. A second dielectric layer if formed over the first dielectric layer and the conductive structure. The pair of electrically conductive contact plugs extend vertically through respective holes in the second dielectric layer. An electrically conductive probe pad is formed upon an upper surface of the second dielectric layer and extends between the pair of contact plugs. Each contact plug is in electrical contact with the probe pad and the electrically conductive structure. During testing, a probe of a measurement device is brought into contact with the probe pad. The measurement device measures the electrical resistance and/or reactance between the probe pad and the semiconductor substrate. The resulting resistance and/or reactance measurement may be compared to an expected resistance and/or reactance value to determine if delamination has occurred at one or more interfaces within the semiconductor wafer.

    摘要翻译： 提出了用于电学确定半导体晶片内的一个或多个界面是否发生分层的装置和方法。 半导体晶片包括在半导体衬底的上表面上的电介质层内形成的测试结构。 测试结构包括导电结构，一对导电接触插塞和探针垫。 导电结构形成在第一电介质层的开口内，与半导体衬底的上表面电接触。 导电结构优选地由用于在半导体晶片内形成互连的所选择的导电材料的相同的垂直堆叠堆叠构成。 如果形成在第一介电层和导电结构上的第二介电层。 一对导电接触插塞通过第二电介质层中的相应孔垂直延伸。 导电探针垫形成在第二电介质层的上表面上并在该对接触插塞之间延伸。 每个接触插塞与探针垫和导电结构电接触。 在测试期间，测量装置的探针与探针垫接触。 测量装置测量探针焊盘和半导体衬底之间的电阻和/或电抗。 可以将所得到的电阻和/或电抗测量与期望的电阻和/或电抗值进行比较，以确定在半导体晶片内的一个或多个界面处是否发生分层。

    On the use of non-spherical carriers for substrate chemi-mechanical polishing
    5.
    发明授权
    On the use of non-spherical carriers for substrate chemi-mechanical polishing 失效
    关于使用非球形载体进行基材化学机械抛光

    公开(公告)号：US5769692A

    公开(公告)日：1998-06-23

    申请号：US772310

    申请日：1996-12-23

    申请人： Nicholas F. Pasch ,  David J. Heine ,  Jayashree Kalpathy Cramer

    发明人： Nicholas F. Pasch ,  David J. Heine ,  Jayashree Kalpathy Cramer

    IPC分类号： B24B37/30 ,  H01L21/306 ,  B24B13/02

    CPC分类号： B24B37/30

    摘要： A substrate holder assembly for immobilizing an integrated circuit (IC) wafer during polishing is described. The substrate holder includes a base plate sized to support the integrated circuit (IC) wafer, a circumferential restraint member arranged with respect to the base plate to engage the IC wafer's edges and a carrier assembly disposed above the base plate and below the IC wafer. The carrier assembly includes a film having a surface that is characterized by a substantially oblate spheroid or hyperboloid surface of rotation, wherein the surface of the film is capable of supporting the IC wafer in a manner causing the IC wafer to bow according to the surface of rotation.

    摘要翻译： 描述了用于在抛光期间固定集成电路（IC）晶片的衬底保持器组件。 衬底保持器包括尺寸适于支撑集成电路（IC）晶片的基板，相对于基板布置以接合IC晶片边缘的周向约束部件和设置在基板上方和IC晶片下方的载体组件。 载体组件包括具有表面的膜，其特征在于基本上为扁圆球形或双曲面的旋转表面，其中膜的表面能够以使IC晶片根据 回转。

    Integrated circuit with tungsten plug containing amorphization layer
    6.
    发明授权
    Integrated circuit with tungsten plug containing amorphization layer 失效
    集成电路与钨丝塞含有非晶化层

    公开(公告)号：US6016009A

    公开(公告)日：2000-01-18

    申请号：US67545

    申请日：1998-04-27

    申请人： Valeriy Y. Sukharev ,  David J. Heine

    发明人： Valeriy Y. Sukharev ,  David J. Heine

    IPC分类号： C23C16/04 ,  C23C16/08 ,  H01L21/285 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76876 ,  C23C16/045 ,  C23C16/08 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877

    摘要： A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

    摘要翻译： 描述了在集成电路（IC）上形成基本上没有接缝形成的钨接触插塞的工艺。 该方法包括在衬底的表面上形成电介质层，在电介质层中形成通孔，在电介质层上覆盖沉积钨的第一体积层并部分地填充通孔，覆盖沉积钨的无定形或微晶层 在钨的第一本体层之上，使得通孔内的钨晶粒的生长被有效地抑制，并且在非晶或微晶层上覆盖沉积钨的第二体层。

    Multistep tungsten CVD process with amorphization step
    7.
    发明授权
    Multistep tungsten CVD process with amorphization step 失效
    多步钨CVD工艺与非晶化步骤

    公开(公告)号：US5804249A

    公开(公告)日：1998-09-08

    申请号：US796945

    申请日：1997-02-07

    申请人： Valeriy Y. Sukharev ,  David J. Heine

    发明人： Valeriy Y. Sukharev ,  David J. Heine

    IPC分类号： C23C16/04 ,  C23C16/08 ,  H01L21/285 ,  H01L21/768 ,  B05D5/12 ,  H01L21/44

    CPC分类号： H01L21/76876 ,  C23C16/045 ,  C23C16/08 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877

    摘要： A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

    摘要翻译： 描述了在集成电路（IC）上形成基本上没有接缝形成的钨接触插塞的工艺。 该方法包括在衬底的表面上形成电介质层，在电介质层中形成通孔，在电介质层上覆盖沉积钨的第一体积层并部分填充通孔，覆盖沉积钨的无定形或微晶层 在钨的第一本体层之上，使得通孔内的钨晶粒的生长被有效地抑制，并且在非晶或微晶层上覆盖沉积钨的第二体层。