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    Synchronous data processing system having arithmetic and control units controlled by single-phase clock pulses
    1.
    发明授权
    Synchronous data processing system having arithmetic and control units controlled by single-phase clock pulses 失效
    具有由单相时钟脉冲控制的算术和控制单元的同步数据处理系统

    公开(公告)号：US4027292A

    公开(公告)日：1977-05-31

    申请号：US536779

    申请日：1974-12-27

    申请人： Kiyokazu Okamoto ,  Masayoshi Isomura ,  Atsuto Kobayashi

    发明人： Kiyokazu Okamoto ,  Masayoshi Isomura ,  Atsuto Kobayashi

    IPC分类号： G06F1/04 ,  G06F7/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/46 ,  G06F12/02 ,  G06F15/16 ,  G06F15/167 ,  G06F7/38 ,  G06F9/06 ,  G06F13/00

    CPC分类号： G06F1/04 ,  G06F9/223

    摘要： A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.

    摘要翻译： 采用单相时钟脉冲的同步数字数据处理系统包括能够在一个时钟脉冲周期期间完成操作的算术和控制单元。 数据处理系统包括封闭数据路径，其中只有一个能够与主/从触发器相同操作的存储器电路的一个阶段用作算术单元中的数据寄存器和控制单元中的地址寄存器。 在任一情况下，在单相时钟脉冲的一个周期期间，在存储器电路中设置输入数据，并且响应于输入数据更新存储器电路的输出。 保持存储器电路的输出直到在下一周期中更新。