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    Integrated circuit pattern designing method, exposure mask manufacturing method, exposure mask, and integrated circuit device manufacturing method
    1.
    发明授权
    Integrated circuit pattern designing method, exposure mask manufacturing method, exposure mask, and integrated circuit device manufacturing method 有权
    集成电路图案设计方法，曝光掩模制造方法，曝光掩模和集成电路器件制造方法

    公开(公告)号：US07131106B2

    公开(公告)日：2006-10-31

    申请号：US10702535

    申请日：2003-11-07

    申请人： Koji Hashimoto ,  Shingo Tokutome ,  Shigeki Nojima

    发明人： Koji Hashimoto ,  Shingo Tokutome ,  Shigeki Nojima

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： There is disclosed a method of designing a pattern of an integrated circuit comprising calculating the window of lithography process on a substrate, the window being calculated at least in partial data of first design data for designing the circuit pattern of integrated circuit, and the window being also calculated in consideration of a specification value of an exposure mask for use in transfer of the circuit pattern, comparing the calculated window of lithography process and the window of lithography process actually required, revising the partial data when the calculated window is smaller than the actually required window, the partial data being revised such that the window of lithography process on the substrate is equal to or larger than the actually required window, and preparing second design data, the second design data being prepared by updating the first design data by using the revised partial data.

    摘要翻译： 公开了一种设计集成电路图案的方法，包括计算衬底上的光刻处理窗口，该窗口至少在第一设计数据的部分数据中计算，用于设计集成电路的电路图案，窗口为 还考虑到用于电路图案的传送的曝光掩模的规格值进行计算，比较计算的光刻工艺窗口和实际需要的光刻工艺窗口，当计算的窗口小于实际的窗口时修改部分数据 修改部分数据，使得基板上的光刻处理窗口等于或大于实际需要的窗口，以及准备第二设计数据，第二设计数据是通过使用第二设计数据来更新第一设计数据 修改部分数据。

    Method of forming a resist pattern
    2.
    发明授权
    Method of forming a resist pattern 失效
    形成抗蚀剂图案的方法

    公开(公告)号：US06333203B1

    公开(公告)日：2001-12-25

    申请号：US09383960

    申请日：1999-08-27

    申请人： Shigeki Nojima ,  Koji Hashimoto

    发明人： Shigeki Nojima ,  Koji Hashimoto

    IPC分类号： H01L2166

    CPC分类号： H01L22/26

    摘要： In a method of forming a resist pattern, a simulation is in advance carried out to select a thickness of the resist film and a thickness of the underlying film to have certain values so that the contrast of the latent image becomes a threshold value or less. The simulation includes the steps of calculating a light intensity profile of a latent image formed in a resist film in a depth direction thereof by an exposure, slicing the light intensity profile of the latent image in the depth direction of the resist film, at a desired position, obtaining a maximum value and a minimum value of light intensity of a latent image at the position where the latent image profile is sliced, calculating a contrast of the latent image on the basis of the maximum and minimum values of the light intensity of the latent image, and determining a thickness of the resist film and a thickness of an underlying film of the resist film to have values so that the contrast becomes a threshold value or less. A resist pattern is then formed on a semiconductor substrate on the basis of the values of the thicknesses determined in the determining step.

    摘要翻译： 在形成抗蚀剂图案的方法中，预先进行模拟以选择抗蚀剂膜的厚度和底层膜的厚度以具有某些值，使得潜像的对比度变为阈值以下。 模拟包括以下步骤：通过曝光来计算在其深度方向上形成在抗蚀剂膜中的潜像的光强度分布，将潜像的深度方向上的潜像的光强度分布切割成期望的步骤 位置，获得在潜像图像被切片的位置处的潜像的光强度的最大值和最小值，基于所述潜像的光强度的最大值和最小值来计算潜像的对比度 潜像，并且确定抗蚀剂膜的厚度和抗蚀剂膜的基底膜的厚度具有使得对比度变为阈值或更小的值的值。 基于在确定步骤中确定的厚度的值，在半导体衬底上形成抗蚀剂图案。

    Semiconductor integrated circuit patterns
    4.
    发明授权
    Semiconductor integrated circuit patterns 失效
    半导体集成电路模式

    公开(公告)号：US06727026B2

    公开(公告)日：2004-04-27

    申请号：US09815004

    申请日：2001-03-23

    申请人： Tatsuaki Kuji ,  Koji Hashimoto ,  Satoshi Usui ,  Shigeki Nojima

    发明人： Tatsuaki Kuji ,  Koji Hashimoto ,  Satoshi Usui ,  Shigeki Nojima

    IPC分类号： G03F900

    CPC分类号： G03F1/36 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of designing patterns of a semiconductor integrated circuit, the shape of each of a plurality of opening patterns formed by a plurality of contact holes is formed into a rectangular shape; and the contact holes are arranged in such a manner that a long side of each of the rectangular opening patterns is opposite to a long side of an adjacent rectangular opening pattern, and the positions of both ends of the long sides are trued up. Furthermore, a photomask is used for manufacturing a semiconductor integrated circuit as designed by the above method of designing patterns of a semiconductor integrated circuit, in which a plurality of rectangular opening patterns are provided thereon as a plurality of rectangular opening patterns for contact holes; and the a plurality of rectangular opening patterns are arranged in such a manner that adjacent long sides thereof are opposite to each other, and the position of both ends of each long side is trued up. Besides, a semiconductor device comprises a semiconductor integrated circuit designed by using a method of designing a semiconductor integrated circuit.

    摘要翻译： 在设计半导体集成电路的图案的方法中，由多个接触孔形成的多个开口图案中的每一个的形状形成为矩形; 并且接触孔被布置成使得每个矩形开口图案的长边与相邻的矩形开口图案的长边相对，并且长边的两端的位置被修整。 此外，光掩模用于制造半导体集成电路，如上述设计的半导体集成电路的图案的方法所设计的，其中多个矩形开口图案设置在其上，作为用于接触孔的多个矩形开口图案; 并且多个矩形开口图案被布置成使得其相邻的长边彼此相对，并且每个长边的两端的位置被修整。 此外，半导体器件包括通过使用设计半导体集成电路的方法设计的半导体集成电路。

    Parameter adjustment method, semiconductor device manufacturing method, and recording medium
    5.
    发明授权
    Parameter adjustment method, semiconductor device manufacturing method, and recording medium 有权
    参数调整方法，半导体器件制造方法和记录介质

    公开(公告)号：US07934175B2

    公开(公告)日：2011-04-26

    申请号：US12062859

    申请日：2008-04-04

    申请人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

    发明人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.

    摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。

    PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM
    7.
    发明申请
    PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM 有权
    参数调整方法，半导体器件制造方法和记录介质

    公开(公告)号：US20080250381A1

    公开(公告)日：2008-10-09

    申请号：US12062859

    申请日：2008-04-04

    申请人： Toshiya KOTANI ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

    发明人： Toshiya KOTANI ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.

    摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在 预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为 参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状 一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于 通过重复计算小于预定的参考值。

    Method for exposure-mask inspection and recording medium on which a program for searching for portions to be measured is recorded
    8.
    发明授权
    Method for exposure-mask inspection and recording medium on which a program for searching for portions to be measured is recorded 失效
    曝光掩模检查和记录介质的方法，其上记录有用于搜索待测量部分的程序

    公开(公告)号：US06334209B1

    公开(公告)日：2001-12-25

    申请号：US09389090

    申请日：1999-09-02

    申请人： Koji Hashimoto ,  Shigeki Nojima

    发明人： Koji Hashimoto ,  Shigeki Nojima

    IPC分类号： G06F1750

    CPC分类号： G03F1/84

    摘要： Disclosed is an exposure mask inspecting method for use in manufacturing semiconductor devices. This inspecting method calculate gradients of a correlation curve of a variation in critical dimension of an exposure mask and a variation in critical dimension of a resist, extracts portions having large slopes of the correlation curve, and slopes the portions having large slopes of the correlation curve as to-be-measured portions at the time of verifying the specifications of the surface critical dimension of the exposure mask.

    摘要翻译： 公开了一种用于制造半导体器件的曝光掩模检查方法。 该检查方法计算曝光掩模的临界尺寸的变化与抗蚀剂的临界尺寸的变化的相关曲线的梯度，提取具有相关曲线的大斜率的部分，并且使具有相关曲线的大斜率的部分倾斜 作为在验证曝光掩模的表面临界尺寸的规格时的待测量部分。