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    STI liner for SOI structure
    1.
    发明申请
    STI liner for SOI structure 有权
    STI衬垫为SOI结构

    公开(公告)号：US20060012004A1

    公开(公告)日：2006-01-19

    申请号：US11221200

    申请日：2005-09-07

    申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L21/76224 ,  H01L21/84

    摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

    摘要翻译： 在制造半导体器件的方法中，提供初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

    STI liner for SOI structure
    2.
    发明授权
    STI liner for SOI structure 有权
    STI衬垫为SOI结构

    公开(公告)号：US06955955B2

    公开(公告)日：2005-10-18

    申请号：US10747494

    申请日：2003-12-29

    申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01

    CPC分类号： H01L21/76224 ,  H01L21/84

    摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

    摘要翻译： 在制造半导体器件的方法中，提供了初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

    STI liner for SOI structure
    4.
    发明授权
    STI liner for SOI structure 有权
    STI衬垫为SOI结构

    公开(公告)号：US07332777B2

    公开(公告)日：2008-02-19

    申请号：US11221200

    申请日：2005-09-07

    申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

    IPC分类号： H01L31/0392

    CPC分类号： H01L21/76224 ,  H01L21/84

    摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

    摘要翻译： 在制造半导体器件的方法中，提供了初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

    Method for forming an SOI structure with improved carrier mobility and ESD protection
    7.
    发明授权
    Method for forming an SOI structure with improved carrier mobility and ESD protection 有权
    用于形成具有改进的载流子迁移率和ESD保护的SOI结构的方法

    公开(公告)号：US07538351B2

    公开(公告)日：2009-05-26

    申请号：US11089405

    申请日：2005-03-23

    申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

    发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

    IPC分类号： H01L29/10

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

    摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

    摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

    FinFET split gate EEPROM structure and method of its fabrication
    8.
    发明授权
    FinFET split gate EEPROM structure and method of its fabrication 有权
    FinFET分裂门EEPROM结构及其制作方法

    公开(公告)号：US07205601B2

    公开(公告)日：2007-04-17

    申请号：US11148903

    申请日：2005-06-09

    申请人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    发明人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

    摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

    摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。 控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。 控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。 选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。 选择门包括第二绝缘层和第二导电层。 绝缘层是覆盖基板和翅片的连续绝缘层的部分。 导电层是形成在绝缘层上的连续导电层的电连续部分。

    FinFET split gate EEPROM structure and method of its fabrication
    9.
    发明申请
    FinFET split gate EEPROM structure and method of its fabrication 有权
    FinFET分裂门EEPROM结构及其制作方法

    公开(公告)号：US20060278915A1

    公开(公告)日：2006-12-14

    申请号：US11148903

    申请日：2005-06-09

    申请人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    发明人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

    摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

    摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。 控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。 控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。 选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。 选择门包括第二绝缘层和第二导电层。 绝缘层是覆盖基板和翅片的连续绝缘层的部分。 导电层是形成在绝缘层上的连续导电层的电连续部分。