公开(公告)号：US6015734A

公开(公告)日：2000-01-18

申请号：US148561

申请日：1998-09-04

申请人： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.

摘要翻译： 实现了当底电极不对准节点接触时，用于形成具有提高的产量的DRAM的叠层电容器的新方法。 沉积平面氧化硅（SiO 2）第一绝缘层，Si 3 N 4蚀刻停止层和一次性第二绝缘层。 在绝缘层中蚀刻用于节点接触的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 节点触点凹陷在第二绝缘层中，但在蚀刻停止层之上，以形成邻接蚀刻停止层的节点触点。 沉积一次性第三SiO 2层。 底部电极的第二个开口被蚀刻到节点触点上。 沉积保形的第二多晶硅层，并在第二开口中化学/机械抛光以形成底部电极。 第三绝缘层和第二绝缘层通过湿法蚀刻去除蚀刻停止层。 当第二开口在节点接触开口上不对准时，邻接Si 3 N 4蚀刻停止层的多晶硅栓保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 通过在底部电极上形成薄的电介质层，并从图案化的第三多晶硅层形成顶部电极来完成电容器。

公开(公告)号：US06307213B1

公开(公告)日：2001-10-23

申请号：US09617427

申请日：2000-07-14

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L2904

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US6121073A

公开(公告)日：2000-09-19

申请号：US24479

申请日：1998-02-17

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。