公开(公告)号：USD690133S1

公开(公告)日：2013-09-24

申请号：US29417487

申请日：2012-04-04

Applicant: Cheng-Ming Wu

Designer： Cheng-Ming Wu

公开(公告)号：US20130233499A1

公开(公告)日：2013-09-12

申请号：US13468299

申请日：2012-05-10

Applicant: Cheng-Ming WU

Inventor： Cheng-Ming WU

IPC: E06B9/38

CPC classification number: E06B9/322 ,  E06B2009/3222

Abstract: Disclosed is a control device for a cordless blind with willful stop at any positions according to user needs during switching operation. The control device primarily comprises a force-return mechanism, a shaft connector, and a braking buffer mechanism which are all installed inside a same housing. The force-return mechanism has a flat spring bevel gear and an elastic element. One end of the shaft connector is a transmission bevel gear meshed with the flat spring bevel gear. The braking buffer mechanism includes a friction ring and an impeding spring where the friction ring is immovably fixed inside the housing with a wear-proof annular inwall. The impeding spring is tightly plugged into the friction ring with an extrusion to prevent the rotation of the transmission bevel gear. Specifically, the shaft connector has a trigger to change the friction between the impeding spring and the friction ring.

Abstract translation: 本发明公开了一种无绳盲板的控制装置，其在切换操作期间根据用户需要在任意位置故意停止。 控制装置主要包括一个力回复机构，一个轴连接器和一个制动缓冲机构，它们均安装在同一个外壳内。 力回复机构具有扁平的弹簧锥齿轮和弹性元件。 轴连接器的一端是与扁平弹簧伞齿轮啮合的传动伞齿轮。 制动缓冲机构包括摩擦环和阻挡弹簧，其中摩擦环通过耐磨环形壁固定在壳体内。 阻碍弹簧用挤压件紧密地插入摩擦环中，以防止变速器锥齿轮的旋转。 具体地，轴连接器具有用于改变阻力弹簧和摩擦环之间的摩擦力的触发器。

公开(公告)号：US06727029B1

公开(公告)日：2004-04-27

申请号：US10336550

申请日：2003-01-02

Applicant: Cheng-Ming Wu ,  Paul Chu ,  Chiou-Sung Chiu ,  Chih-Wing Chang

Inventor： Cheng-Ming Wu ,  Paul Chu ,  Chiou-Sung Chiu ,  Chih-Wing Chang

IPC: G03F900

CPC classification number: G03F1/64

Abstract: A reticle for holding a mask thereon with reduced particle contamination problem is described. The reticle is constructed by a base plate that is formed of an optically transparent material such as quartz and has a recessed slot in a top surface to enclose an area at least the size of a mask formed on the base plate. An adhesive partially fills the recessed slot such that a top surface of the adhesive is at least 0.5 mm below the top surface of the base plate. A pellicle frame is mounted in the recessed slot with a bottom end of the frame encased in the adhesive and a thin film covering the top end of the pellicle frame to from a hermetically sealed cavity for protecting the mask.

Abstract translation: 描述了用于在其上保持减少的颗粒污染问题的掩模上的掩模版。 掩模版由基板构成，该基板由诸如石英的光学透明材料形成，并且在顶表面中具有凹槽，以至少包围形成在基板上的掩模的尺寸的区域。 粘合剂部分地填充凹槽，使得粘合剂的顶表面在基板的顶表面下方至少0.5mm。 防护薄膜组件框架安装在凹槽中，框架的底端封装在粘合剂中，并且薄膜覆盖防护薄膜组件框架的顶端，以从密封的腔体中保护面罩。

公开(公告)号：US06168989A

公开(公告)日：2001-01-02

申请号：US09318924

申请日：1999-05-26

Applicant: Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

Inventor： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L27/10814

Abstract: A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.

Abstract translation: 描述了使用用于DRAM单元的新的和改进的冠蚀刻窗口工艺制造冠电容器的方法。 在形成用于存储单元的FET之后，形成平面的第一绝缘层（IPO-1），并在其上形成位线。 沉积第二绝缘层（IPO-2），并沉积第一蚀刻停止层和一次性绝缘层。 接触开口在层中蚀刻到衬底上，并且填充有多晶硅以形成电容器节点接触插塞。 去除一次性层以暴露在第一蚀刻停止层上方延伸的插塞的上部。 沉积第二蚀刻停止层，并且沉积厚的绝缘层，其中电容器开口被蚀刻到插头上。 电容器开口可以在厚的绝缘层中过蚀刻，因为插头向上延伸，从而允许所有的插头暴露在晶片上，而不会过滤掉底层的IPO-2层，否则会导致电容器对位线短路， 底部电极形成在电容器开口中。

公开(公告)号：US06323118B1

公开(公告)日：2001-11-27

申请号：US09114129

申请日：1998-07-13

Applicant: Cheng-Yeh Shih ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu

Inventor： Cheng-Yeh Shih ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu

IPC: H01L214763

CPC classification number: H01L21/76816 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76811 ,  H01L21/76813

Abstract: A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings. The openings in the first and second etch-stop layers are both extended by etching the second and first dielectric layers, respectively, until the former opening reaches the second etch-stop layer, and the latter reaches the underlying substructure of devices within the semiconductor substrate. Thus, a combination of contact via interconnects, without borders, and self-aligned with respect to metal lines with relaxed photolithographic tolerances is formed together and simultaneously using a modified dual damascene process having two etch-stop layers.

Abstract translation: 公开了一种用于使用具有两个蚀刻停止层的改进的双镶嵌工艺在一起形成自对准，无边界接触和通孔同时具有松弛光刻对准公差的方法。 在第一介电层上形成第一蚀刻停止层。 接下来在第一蚀刻停止层上依次形成第二介电层和第二蚀刻停止层。 使用第一光致抗蚀剂层将接触/通孔图案蚀刻到第一蚀刻停止层中。 在接触/经过图案化的第一蚀刻停止层上形成第二光致抗蚀剂层，其上形成有金属线沟槽图案。 接触/通孔开口被蚀刻到第一介电层中，直到达到第二蚀刻停止层。 然后，通过开口蚀刻第一和第二蚀刻停止层。 第一和第二蚀刻停止层中的开口都分别通过蚀刻第二和第一电介质层而延伸，直到前一个开口到达第二蚀刻停止层，并且后者到达半导体衬底内的器件的底层子结构 。 因此，一起形成了具有无边界的接触通孔互连和相对于具有松弛光刻公差的金属线自对准的组合，并且同时使用具有两个蚀刻停止层的改进的双镶嵌工艺。

公开(公告)号：US06265315B1

公开(公告)日：2001-07-24

申请号：US09104030

申请日：1998-06-24

Applicant: Yu-Hua Lee ,  James (Cheng-Ming) Wu

Inventor： Yu-Hua Lee ,  James (Cheng-Ming) Wu

IPC: H01L21302

CPC classification number: H01L21/76819 ,  H01L21/31055

Abstract: A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal first insulating layer that is uniformly thick across the substrate. An etch-stop composed of Si3N4 is deposited and a second insulating layer, composed of SiO2 or a low-dielectric-constant insulator, is deposited. The second insulating layer is then partially chemically/mechanically polished back to within a few thousand Angstroms of the etch-stop layer. The remaining second insulating layer is then plasma etched back selectively to the etch-stop layer to form a planar surface having a uniformly thick first insulating layer over the electrically conducting lines. The contact openings or via holes can now etched to a uniform depth in the etch-stop layer and the first insulating layer across the substrate. This results in contact openings having a constant aspect ratio across the substrate, thereby resulting in more repeatable and reliable contact resistance (Rc).

Abstract translation: 实现了一种在图案化的导电层上制造平面层间电介质（ILD）层的方法，该层具有改善的跨衬底表面的均匀度。 该方法包括形成导电线，在其上沉积跨基板均匀厚的共形第一绝缘层。 沉积由Si 3 N 4构成的蚀刻停止层，并沉积由SiO 2或低介电常数绝缘体组成的第二绝缘层。 然后将第二绝缘层部分地化学/机械抛光回到蚀刻停止层的几千埃内。 然后将剩余的第二绝缘层等离子体蚀刻回蚀刻停止层，以形成在导电线上具有均匀厚的第一绝缘层的平坦表面。 接触开口或通孔现在可以在蚀刻停止层和穿过基底的第一绝缘层上蚀刻到均匀的深度。 这导致在基板上具有恒定纵横比的接触开口，从而导致更可重复和可靠的接触电阻（Rc）。

公开(公告)号：US06235580B1

公开(公告)日：2001-05-22

申请号：US09467123

申请日：1999-12-20

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process for forming crown shaped capacitor structures, for a DRAM device, has been developed. The process features the use of a disposable insulator layer, applied prior to photolithographic and dry etching procedures, used to define the capacitor upper plate structures. The disposable insulator layer alleviates the topography effects presented by crown shaped storage node structures, relaxing the complexity of the patterning of the capacitor upper plate structures.

Abstract translation: 已经开发了用于形成用于DRAM器件的冠形电容器结构的工艺。 该方法的特征在于使用一次性绝缘体层，其在光刻和干蚀刻工艺之前施加，用于限定电容器上板结构。 一次性绝缘体层减轻了冠形存储节点结构呈现的形貌效应，减轻了电容器上板结构图案化的复杂性。

公开(公告)号：US5989784A

公开(公告)日：1999-11-23

申请号：US55463

申请日：1998-04-06

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

IPC: H01L21/768 ,  H01L23/525 ,  G03F7/40 ,  B44C1/22 ,  C03C15/00 ,  C25F3/00

CPC classification number: H01L23/5258 ,  H01L21/76802 ,  H01L2924/0002

Abstract: A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.

Abstract translation: 使用专门的2级蚀刻工艺在保险丝开口（或窗口）92中的熔丝16上方形成蚀刻停止层40的方法。 本发明具有两个重要特征：首先，蚀刻停止层40由用于在基板上制造半导体器件的多晶硅层（P2或P4）形成。 蚀刻停止层40优选由多晶硅层形成，用于从接触到衬底10（P2）或形成电容器（P4）的一部分。 第二，使用专门的两级蚀刻工艺，其中第二阶段蚀刻蚀刻停止层40，同时在金属焊盘85上形成钝化层114.该方法包括：在保险丝区域15上方的所述隔离区域10上形成保险丝16 ; 形成覆盖保险丝16的第一电介质层30; 在第一介电层30上形成蚀刻停止层40; 在所述蚀刻停止层上形成绝缘层43; 在绝缘层43中通过在第一蚀刻阶段中蚀刻完整的熔融光致抗蚀剂开口90A并停止蚀刻停止层40上的第一蚀刻阶段来在绝缘层43中形成熔丝开口92; 并且在第二蚀刻阶段通过熔丝开口92中的蚀刻停止层40进行蚀刻。

公开(公告)号：US5985765A

公开(公告)日：1999-11-16

申请号：US75368

申请日：1998-05-11

Applicant: Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/525 ,  H01L21/00

CPC classification number: H01L24/02 ,  H01L23/5256 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14

Abstract: A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.

Abstract translation: 当接触开口被蚀刻到接合焊盘时，使用覆盖层来实现减少焊盘损耗的方法，同时将更深的熔丝开口蚀刻到衬底。 在集成电路半导体芯片的顶面上使用接合焊盘以提供用于I / O和电源的外部电连接。 并且在底层绝缘层中使用熔丝来去除冗余的有缺陷的电路元件，从而修复有缺陷的芯片。 将钝化层中的接触开口蚀刻到芯片顶表面附近的接合焊盘是合乎需要的（成本有效的），同时蚀刻保险丝上较厚的下层绝缘层中更深的熔丝开口。 然而，由于两种类型的开口的蚀刻深度的差异，由Al / Cu组成的焊盘通常是过蚀刻的，导致焊盘可靠性问题。 本发明使用了一种新颖的方法，其中在焊盘上形成具有低蚀刻速率的覆盖层，以防止在较厚绝缘层中将熔丝开口蚀刻到所需深度时的过蚀刻。

公开(公告)号：US20120180014A1

公开(公告)日：2012-07-12

申请号：US13277229

申请日：2011-10-20

Applicant: Min-Yi Fang ,  Ssu-Ping Ko ,  Cheng-Ming Wu ,  Chun-Chen Chen ,  Tsung-Ching Lu ,  Tung-Chieh Chen ,  Yu-Chi Su

Inventor： Min-Yi Fang ,  Ssu-Ping Ko ,  Cheng-Ming Wu ,  Chun-Chen Chen ,  Tsung-Ching Lu ,  Tung-Chieh Chen ,  Yu-Chi Su

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A computer-implemented method to perform context-sensitive incremental design rule checking (DRC) for an integrated circuit (IC). An incremental DRC engine checks design rule violations between a set of environment shapes and a set of active shapes. If no design rule violations are found, the set of active shapes will be added into the set of environment shapes. Furthermore, the incremental DRC engine can be embedded into placement tools, routing tools, or interactive layout editing tools to check design rule violations and help generate DRC error free layouts.

Abstract translation: 一种用于为集成电路（IC）执行上下文敏感增量设计规则检查（DRC）的计算机实现的方法。 增量DRC引擎检查一组环境形状和一组活动形状之间的设计规则违规。 如果没有发现违规设计规则，那么活动形状集将被添加到一组环境形状中。 此外，增量DRC引擎可以嵌入到布局工具，路由工具或交互式布局编辑工具中，以检查违规设计规则，并帮助生成DRC无错误布局。