公开(公告)号：US07619166B2

公开(公告)日：2009-11-17

申请号：US11136558

申请日：2005-05-25

申请人： Kuo-Ching Huang ,  Yu-Cheng Chang

发明人： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC分类号： H01B7/08

CPC分类号： H05K1/147 ,  H04N1/00519 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0081 ,  H05K1/144 ,  H05K2201/09109

摘要： A bus structure may include two or more soft buses and one or more soft separation layers. The two or more soft buses may be stacked side by side with respect to each other. The one or more soft separation layers may be sandwiched between two adjacent soft buses of the two or more soft buses.

摘要翻译： 总线结构可以包括两个或更多个软总线和一个或多个软分离层。 两个以上的软总线可以相对于彼此并排堆叠。 一个或多个软分离层可以夹在两个或多个软总线的两个相邻的软总线之间。

公开(公告)号：US20070129189A1

公开(公告)日：2007-06-07

申请号：US11332340

申请日：2006-01-17

申请人： Kuo-Ching Huang ,  Yu-Cheng Chang

发明人： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC分类号： F16H7/18 ,  F16H7/08

CPC分类号： F16H7/08 ,  F16H2007/0806 ,  F16H2007/0812

摘要： A belt tension adjustment mechanism for use in an optical module of a scanning apparatus includes a sliding member, a fixture member, a supporting member and a resilient member. The sliding member is arranged on a surface of the optical module and movable on the surface of the optical module. The fixture member is used to fix the belt. The supporting member supports the belt. By means of the resilient member, a tension is applied onto the belt.

摘要翻译： 用于扫描装置的光学模块中的皮带张力调节机构包括滑动构件，固定构件，支撑构件和弹性构件。 滑动构件布置在光学模块的表面上并且可在光学模块的表面上移动。 固定件用于固定皮带。 支撑构件支撑带。 通过弹性构件，张力被施加到带上。

公开(公告)号：US20060164531A1

公开(公告)日：2006-07-27

申请号：US11044922

申请日：2005-01-27

申请人： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

发明人： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC分类号： H04N5/335

CPC分类号： H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

摘要： A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

摘要翻译： 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US06880675B2

公开(公告)日：2005-04-19

申请号：US10423607

申请日：2003-04-25

申请人： Kuo-Ching Huang

发明人： Kuo-Ching Huang

IPC分类号： E06C1/18 ,  E06C1/22 ,  E06C7/08 ,  E06C1/00

CPC分类号： E06C7/083 ,  E06C1/18 ,  E06C1/22

摘要： A ladder assembly includes two symmetric support stands pivotally connected with each other. Each of the two support stands includes a main frame, an upper frame, a lower frame, a top bar, a retraction control unit, and four fixing devices. Thus, height of the ladder assembly can be adjusted easily and conveniently, thereby facilitating the user operating the ladder assembly. In addition, the upper frame and the lower frame can be folded on the main frame, so as to reduce the volume the ladder assembly efficiently, thereby greatly facilitating storage and transportation of the ladder assembly.

摘要翻译： 梯子组件包括彼此枢转连接的两个对称支撑架。 两个支撑台中的每一个包括主框架，上框架，下框架，顶杆，缩回控制单元和四个固定装置。 因此，可以容易且方便地调整梯子组件的高度，从而便于使用者操作梯子组件。 此外，上框架和下框架可以折叠在主框架上，以便有效地减少梯子组件的体积，从而极大地方便了梯子组件的存储和运输。

公开(公告)号：US06661043B1

公开(公告)日：2003-12-09

申请号：US10400401

申请日：2003-03-27

申请人： Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

发明人： Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L27/1087

摘要： A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.

摘要翻译： 提供了一种用于创建1T RAM单元的新方法。 施加标准处理以在衬底的表面中产生STI沟槽，在STI沟槽的侧壁中进行N2注入。 产生衬里氧化层，注入的N 2与衬里氧化物相互作用以在STI沟槽的暴露表面上形成SiON。 沉积和抛光STI氧化物，在那里填充STI沟槽。 进行冠图案化以限定电容器区域，冠图案停止在蚀刻停止材料层上，并且所产生的SION并且部分地从STI沟槽去除STI氧化物。 蚀刻停止材料层，暴露的SiON和衬垫氧化物层被去除，暴露硅衬底的表面，STI氧化物的蚀刻层不受该去除的影响。 生长一层SAC氧化物，n阱和p阱注入进行到衬底的表面。 去除SAC氧化物层，生长栅极氧化物，沉积多晶硅并进行图案化和蚀刻，形成电容器的多晶硅栅极材料和多晶硅顶板。 进一步应用标准处理，通过为栅电极提供栅极间隔物和杂质注入，通过对接触表面进行喷淋并且通过提供与电池的接触点的接触来完成1T-RAM单元。

公开(公告)号：US06307213B1

公开(公告)日：2001-10-23

申请号：US09617427

申请日：2000-07-14

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L2904

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US06271570B1

公开(公告)日：2001-08-07

申请号：US09578414

申请日：2000-05-26

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US06174802B1

公开(公告)日：2001-01-16

申请号：US09342042

申请日：1999-06-28

申请人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

发明人： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Min-Hsiung Chiang

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： A method for forming a self aligned contact without key holes using a two step contact deposition. The process begins by providing a semiconductor structure having conductive structures (such as bit lines) thereover with sidewalls and having a contact area adjacent to the conductive structures. The conductive structures comprise at least one conductive layer with a hard mask thereover. A spacer layer is formed over the hard mask and the substrate structure and anisotropically etched to form sidewall spacers on the sidewalls of the conductive structure. A second dielectric (IPO) layer is formed over the sidewall spacers, the hard mask, and the substrate structure, whereby the second dielectric layer has a keyhole. A contact opening is formed in the second dielectric layer over the contact area. A first contact layer having poor step coverage is formed in the contact openings and over the second dielectric layer, thereby plugging the keyhole without filling it. A second contact layer is formed over the first contact layer.

摘要翻译： 使用两步接触沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有导电结构（例如位线）的半导体结构，其具有侧壁并且具有与导电结构相邻的接触区域。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和衬底结构之上形成间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成侧壁间隔物。 在侧壁间隔物，硬掩模和基板结构上方形成第二电介质层（IPO），由此第二介电层具有锁孔。 在接触区域上的第二电介质层中形成接触开口。 在接触开口和第二电介质层上形成具有差的台阶覆盖率的第一接触层，从而在不填充锁孔的情况下封闭钥匙孔。 在第一接触层上形成第二接触层。

公开(公告)号：US6121073A

公开(公告)日：2000-09-19

申请号：US24479

申请日：1998-02-17

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US6110822A

公开(公告)日：2000-08-29

申请号：US47539

申请日：1998-03-25

申请人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Dun-Nian Yaung

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/44 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11 ,  H01L21/76838 ,  H01L27/1108 ,  H01L21/2022

摘要： A method of forming a contact in a thin film transistor with a gate electrode and an interconnect formed on a substrate, in an SRAM device comprises the following steps. Form a gate oxide layer over device. Form a split amorphous silicon layer over gate oxide layer. Form a cap layer over split amorphous silicon layer. Form a contact opening down to interconnect. Form contact metallization in opening on the surface of interconnect either as a blanket titanium layer followed by rapid thermal anneal to form a silicide and stripping unreacted titanium or by selective formation of a tungsten metal silicide in the opening. Strip cap layer from device. Form a second amorphous silicon layer on split silicon layer. Recrystallize silicon layers to form a polysilicon channel layer from amorphous silicon layers. Dope regions of polysilicon channel layer aside from a channel region above gate electrode.

摘要翻译： 在SRAM器件中，在具有形成在衬底上的栅极和互连的薄膜晶体管中形成接触的方法包括以下步骤。 在器件上形成栅氧化层。 在栅极氧化层上形成分裂的非晶硅层。 在分裂的非晶硅层上形成覆盖层。 形成一个联系人开放互连。 在互连表面上开口形成接触金属化，作为覆盖钛层，随后快速热退火以形成硅化物并汽提未反应的钛或通过在开口中选择性形成钨金属硅化物。 从设备剥去盖帽层。 在分裂硅层上形成第二非晶硅层。 重新结晶硅层以形成来自非晶硅层的多晶硅沟道层。 多晶硅沟道层的掺杂区域与栅电极上方的沟道区域不同。