公开(公告)号：US07193441B2

公开(公告)日：2007-03-20

申请号：US10993054

申请日：2004-11-18

申请人： Kuo-Ji Chen ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Ker-Min Chen

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/00384

摘要： A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

摘要翻译： 耦合在高电压电路和低电压电路之间的输入/输出缓冲电路中使用的高压缓冲器模块在第一电源电压和其互补的第二电源电压之间工作。 耦合在第一电源电压和输出节点之间的上拉模块响应于输入信号将第一电源电压输出到输出节点。 电压检测电路为上拉模块提供从预定的一组电压电平选择的至少一个偏置电压，其中电压检测电路在检测到第一电源电压的降低时选择偏置电压。

公开(公告)号：US07151391B2

公开(公告)日：2006-12-19

申请号：US10852390

申请日：2004-05-24

申请人： Ker-Min Chen ,  Kuo-Ji Chen

发明人： Ker-Min Chen ,  Kuo-Ji Chen

IPC分类号： H03K19/0175

CPC分类号： H03K3/356113 ,  H03K17/102

摘要： An integrated circuit for level-shifting voltage signals comprising an input/output pad, and an input/output circuit coupled to the output pad having a plurality of devices operating with a bias supply voltage operable to shift between the range of the bias supply voltage to the range of an input/output supply voltage that is higher than the bias supply voltage is provided. In addition, an integrated circuit comprises an input circuit coupled to an input pad operable to input shift signals from an input/output supply voltage range to a core supply voltage range, an output circuit coupled to an output pad operable to shift output signals from a bias supply voltage range to an input/output supply voltage range, and a core circuit coupled to the input and output circuits and having a gate dielectric thickness substantially similar to a gate dielectric thickness of the input circuit and the output circuit.

摘要翻译： 一种用于电平移动电压信号的集成电路，包括输入/​​输出焊盘以及耦合到输出焊盘的输入/输出电路，该输出/输出电路具有多个器件，工作在偏置电源电压下工作，该偏置电源电压可操作以在偏置电源电压的范围 提供高于偏置电源电压的输入/输出电源电压的范围。 此外，集成电路包括耦合到输入焊盘的输入电路，其可操作以将输入/输出电源电压范围的移位信号输入到核心电源电压范围;耦合到输出焊盘的输出电路，其可操作以将输出信号从 偏置电源电压范围到输入/输出电源电压范围，以及耦合到输入和输出电路的核心电路，并且具有基本上类似于输入电路和输出电路的栅介质厚度的栅介质厚度。

公开(公告)号：US20060186921A1

公开(公告)日：2006-08-24

申请号：US11063961

申请日：2005-02-23

申请人： Kuo-Ji Chen ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Ker-Min Chen

IPC分类号： H03K19/00

CPC分类号： H03K19/0016 ,  H03K19/0013 ,  H03K19/09429

摘要： A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

摘要翻译： 双电压三态缓冲器电路控制后驱动电路以三态模式工作，并且包括在低电源电压下工作的三态逻辑控制模块，用于从三端接收一个或多个输入的电平转换器 状态逻辑控制模块，并且用于控制电平移位器的两个差分输出的输出控制电路和由电平移位器的两个差分输出驱动的后驱动电路，其中电平移位器，输出控制电路， 后驱动器电路在高电源电压下工作，并且其中当三态逻辑控制模块产生用于将后驱动电路置于高阻态的输入时，输出控制电路与电平移位器一起工作以关断PMOS 和后驱动电路的NMOS晶体管，同时将电平移位器与高电源电压隔离。

公开(公告)号：US07248076B2

公开(公告)日：2007-07-24

申请号：US11063961

申请日：2005-02-23

申请人： Kuo-Ji Chen ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Ker-Min Chen

IPC分类号： H03K19/0175

CPC分类号： H03K19/0016 ,  H03K19/0013 ,  H03K19/09429

摘要： A dual-voltage three-state buffer circuit controls a post driver circuit to operate in a three-state mode and includes a tri-state logic control module operated under a low supply voltage, a level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling two differential outputs of the level shifter, and a post driver circuit driven by the two differential outputs of the level shifter, wherein the level shifter, the output control circuit, an the post driver circuit are operated under a high supply voltage, and wherein when the tri-state logic control module generates the inputs for putting the post driver circuit in a high impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage.

摘要翻译： 双电压三态缓冲器电路控制后驱动电路以三态模式工作，并且包括在低电源电压下工作的三态逻辑控制模块，用于从三端接收一个或多个输入的电平转换器 状态逻辑控制模块，并且用于控制电平移位器的两个差分输出的输出控制电路和由电平移位器的两个差分输出驱动的后驱动电路，其中电平移位器，输出控制电路， 后驱动器电路在高电源电压下工作，并且其中当三态逻辑控制模块产生用于将后驱动电路置于高阻态的输入时，输出控制电路与电平移位器一起工作以关断PMOS 和后驱动电路的NMOS晶体管，同时将电平移位器与高电源电压隔离。

公开(公告)号：US07173472B2

公开(公告)日：2007-02-06

申请号：US10859726

申请日：2004-06-03

申请人： Kuo-Ji Chen ,  Tsung-Hsin Yu ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Tsung-Hsin Yu ,  Ker-Min Chen

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/0027

摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

摘要翻译： 提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。 缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。 逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。 反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。 调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。 缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。

公开(公告)号：US20100026366A1

公开(公告)日：2010-02-04

申请号：US12494082

申请日：2009-06-29

申请人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

发明人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

摘要翻译： 公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管 ，源极连接到地（VSS）的NMOS晶体管和连接到在VCCL和VSS之间摆动的第一信号的栅极，以及耦合在一对PMOS晶体管之一的漏极和 NMOS晶体管，其中一对PMOS晶体管是高压晶体管，并且当VCCL低于预定电压电平时，开关器件关断，并且当VCCL高于预定电压电平时，开关器件导通。

公开(公告)号：US20050270079A1

公开(公告)日：2005-12-08

申请号：US10859726

申请日：2004-06-03

申请人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

IPC分类号： H03K5/153 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/0027

摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

摘要翻译： 提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。 缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。 逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。 反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。 调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。 缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。

公开(公告)号：US07884643B2

公开(公告)日：2011-02-08

申请号：US12494082

申请日：2009-06-29

申请人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

发明人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

IPC分类号： H03K19/094

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

摘要翻译： 公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管 ，源极连接到地（VSS）的NMOS晶体管和连接到在VCCL和VSS之间摆动的第一信号的栅极，以及耦合在一对PMOS晶体管之一的漏极和 NMOS晶体管，其中一对PMOS晶体管是高压晶体管，并且当VCCL低于预定电压电平时，开关器件关断，并且当VCCL高于预定电压电平时，开关器件导通。

公开(公告)号：US20060103435A1

公开(公告)日：2006-05-18

申请号：US10993054

申请日：2004-11-18

申请人： Kuo-Ji Chen ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Ker-Min Chen

IPC分类号： H03K3/00

CPC分类号： H03K19/00315 ,  H03K19/00384

摘要： A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

摘要翻译： 耦合在高电压电路和低电压电路之间的输入/输出缓冲电路中使用的高压缓冲器模块在第一电源电压和其互补的第二电源电压之间工作。 耦合在第一电源电压和输出节点之间的上拉模块响应于输入信号将第一电源电压输出到输出节点。 电压检测电路为上拉模块提供从预定的一组电压电平选择的至少一个偏置电压，其中电压检测电路在检测到第一电源电压的降低时选择偏置电压。

公开(公告)号：US09293606B2

公开(公告)日：2016-03-22

申请号：US13296410

申请日：2011-11-15

申请人： Kuo-Ji Chen ,  Wei Yu Ma ,  Ta-Pen Guo ,  Hsien-Wei Chen ,  Hao-Yi Tsai

发明人： Kuo-Ji Chen ,  Wei Yu Ma ,  Ta-Pen Guo ,  Hsien-Wei Chen ,  Hao-Yi Tsai

IPC分类号： H01L29/93 ,  H01L29/94 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L29/93 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/585 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.

摘要翻译： 用于半导体器件的密封环设置有嵌入式去耦电容器。 密封环外围围绕密封环区域中的集成电路芯片。 至少一个嵌入式去耦电容器可以包括MOS电容器，变容二极管，MOM电容器和具有多个电容器板耦合在一起的叉指电容器。 相对的电容器板耦合到不同的电位，并且可以有利地耦合到Vdd和Vss。