公开(公告)号：US08822299B2

公开(公告)日：2014-09-02

申请号：US13038663

申请日：2011-03-02

申请人： Kwangwook Lee ,  Inseak Hwang

发明人： Kwangwook Lee ,  Inseak Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/36 ,  H01L29/772 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

摘要翻译： 一种制造半导体器件的方法包括：形成包含氧化物的栅极电介质层和在衬底上的至少一个导电层，在导电层上形成掩模，并通过蚀刻所述至少一个导电层来图案化所述至少一个导电层 使用掩模作为蚀刻掩模从而形成栅电极，其中选择栅介质层的氧化物和至少一个导电层的材料，使得形成的至少一个导电层的蚀刻副产物形成 在蚀刻所述至少一个导电层期间在掩模上包含相对于蚀刻剂具有比栅极电介质层的氧化物更高的蚀刻速率的氧化物。

公开(公告)号：US20110215421A1

公开(公告)日：2011-09-08

申请号：US13038663

申请日：2011-03-02

申请人： Kwangwook Lee ,  Inseak Hwang

发明人： Kwangwook Lee ,  Inseak Hwang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/36 ,  H01L29/772 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

摘要翻译： 一种制造半导体器件的方法包括：形成包含氧化物的栅极电介质层和在衬底上的至少一个导电层，在导电层上形成掩模，并通过蚀刻所述至少一个导电层来图案化所述至少一个导电层 使用掩模作为蚀刻掩模从而形成栅电极，其中选择栅介质层的氧化物和至少一个导电层的材料，使得形成的至少一个导电层的蚀刻副产物形成 在蚀刻所述至少一个导电层期间在掩模上包含相对于蚀刻剂具有比栅极电介质层的氧化物更高的蚀刻速率的氧化物。