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    SEMICONDUCTOR MEMORY DEVICE AND EMTHOD OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND EMTHOD OF FORMING THE SAME 审中-公开
    半导体存储器件和形成其的EMTHOD

    公开(公告)号：US20120139028A1

    公开(公告)日：2012-06-07

    申请号：US13302676

    申请日：2011-11-22

    申请人： Jongchul Park ,  Inseak Hwang ,  Sangsup Jeong

    发明人： Jongchul Park ,  Inseak Hwang ,  Sangsup Jeong

    IPC分类号： H01L29/792 ,  H01L27/092

    CPC分类号： H01L27/10876 ,  H01L27/0207

    摘要： A semiconductor memory device includes a device isolation pattern defining an active region of a substrate, a buried gate electrode extending longitudinally in a given direction across the active region, a first impurity region and a second impurity region disposed along respective sides of the buried gate electrode, a conductive pad disposed on the substrate and electrically connected to the first impurity region, a first contact plug disposed on the substrate and electrically connected to the second impurity doping region, and a second contact plug disposed on the pad.

    摘要翻译： 半导体存储器件包括限定衬底的有源区的器件隔离图案，跨过有源区沿给定方向纵向延伸的掩埋栅电极，沿掩埋栅电极的相应侧设置的第一杂质区和第二杂质区 设置在所述基板上并电连接到所述第一杂质区的导电焊盘，设置在所述基板上并电连接到所述第二杂质掺杂区的第一接触插塞和设置在所述焊盘上的第二接触插塞。

    SEMICONDUCTOR DEVICES HAVING PLANARIZED INSULATION LAYERS AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES HAVING PLANARIZED INSULATION LAYERS AND METHODS OF FABRICATING THE SAME 审中-公开
    具有平面绝缘层的半导体器件及其制造方法

    公开(公告)号：US20120214316A1

    公开(公告)日：2012-08-23

    申请号：US13398895

    申请日：2012-02-17

    申请人： Jin-Woo Bae ,  Inseak Hwang ,  Myangsik Han ,  Se Jung Park ,  Sung-Min Cho ,  YoungHo Koh ,  Yi Koan Hong

    发明人： Jin-Woo Bae ,  Inseak Hwang ,  Myangsik Han ,  Se Jung Park ,  Sung-Min Cho ,  YoungHo Koh ,  Yi Koan Hong

    IPC分类号： H01L21/31

    CPC分类号： H01L21/31053 ,  H01L21/76819

    摘要： A semiconductor device and a method of fabricating a semiconductor device including a step of providing a substrate having a first region and a second region adjacent to each other, a step of forming a structure on the substrate in the first region, the structure including a top surface and a sidewall, a step of forming a first insulation layer on the substrate including the structure, the first insulation layer including a first top surface in the first region, an inclined sidewall on the sidewall of structure, and a second top surface in the second region, a step of forming a second insulation layer on the first insulation layer, and a step of planarizing the second and first insulation layers to form a common planarized surface.

    摘要翻译： 一种半导体器件和制造半导体器件的方法，包括提供具有彼此相邻的第一区域和第二区域的衬底的步骤，在所述第一区域中在所述衬底上形成结构的步骤，所述结构包括顶部 表面和侧壁，在包括所述结构的所述基板上形成第一绝缘层的步骤，所述第一绝缘层包括所述第一区域中的第一顶表面，所述结构的侧壁上的倾斜侧壁和所述第二绝缘层中的第二顶表面 第二区域，在第一绝缘层上形成第二绝缘层的步骤，以及平坦化第二绝缘层和第一绝缘层以形成共同的平坦化表面的步骤。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20160336327A1

    公开(公告)日：2016-11-17

    申请号：US15093033

    申请日：2016-04-07

    申请人： Jonghyuk PARK ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

    发明人： Jonghyuk PARK ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

    IPC分类号： H01L27/108 ,  H01L21/66

    CPC分类号： H01L27/10855 ,  H01L22/30 ,  H01L22/34 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876

    摘要： A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

    摘要翻译： 制造半导体器件的方法包括提供包括一对第一区域和其间的第二区域的衬底，在相应的第一区域上形成第一图案以至少部分地限定第二区域的阶梯部分，并且形成虚设图案， 至少部分地填充逐步部分。 虚拟图案可以是电浮置结构。 伪图案可以形成为在相应的第一区域上形成第二图案的一部分，并且虚设图案和第二图案可以包括基本上共同的材料。 由于虚拟图案至少部分地填充第二区域的逐步部分，所以覆盖第二图案和虚设图案的材料层可以省略相应的逐步部分。

    Method of fabricating semiconductor device
    10.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08822299B2

    公开(公告)日：2014-09-02

    申请号：US13038663

    申请日：2011-03-02

    申请人： Kwangwook Lee ,  Inseak Hwang

    发明人： Kwangwook Lee ,  Inseak Hwang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/36 ,  H01L29/772 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

    摘要翻译： 一种制造半导体器件的方法包括：形成包含氧化物的栅极电介质层和在衬底上的至少一个导电层，在导电层上形成掩模，并通过蚀刻所述至少一个导电层来图案化所述至少一个导电层 使用掩模作为蚀刻掩模从而形成栅电极，其中选择栅介质层的氧化物和至少一个导电层的材料，使得形成的至少一个导电层的蚀刻副产物形成 在蚀刻所述至少一个导电层期间在掩模上包含相对于蚀刻剂具有比栅极电介质层的氧化物更高的蚀刻速率的氧化物。