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    UNDER-RUN COMPENSATION CIRCUIT, METHOD THEREOF, AND APPARATUSES HAVING THE SAME
    1.
    发明申请
    UNDER-RUN COMPENSATION CIRCUIT, METHOD THEREOF, AND APPARATUSES HAVING THE SAME 审中-公开
    欠压补偿电路及其方法及具有该功能的装置

    公开(公告)号：US20120075262A1

    公开(公告)日：2012-03-29

    申请号：US13206704

    申请日：2011-08-10

    申请人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

    发明人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

    IPC分类号： G09G5/00

    CPC分类号： G09G5/363

    摘要： An under-run compensation circuit is provided. The under-run compensation circuit is configured to receive a clock signal, data, and an under-run detection signal that indicates whether or not an under-run is occurring. The under-run compensation circuit is further configured to output the clock signal and the data when receiving the under-run detection signal that indicates that an under-run is not occurring. The under-run compensation circuit is additionally configured to output the clock signal and dummy data when receiving the under- run detection signal that indicates that an under-run is occurring.

    摘要翻译： 提供欠运行补偿电路。 欠运行补偿电路被配置为接收指示是否发生欠运行的时钟信号，数据和欠运行检测信号。 欠运行补偿电路还被配置为当接收到指示未发生欠运行的欠运行检测信号时输出时钟信号和数据。 欠运行补偿电路还被配置为当接收到指示发生欠运行的欠运行检测信号时输出时钟信号和伪数据。

    PROCESSOR, DATA PROCESSING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE PROCESSOR
    2.
    发明申请
    PROCESSOR, DATA PROCESSING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE PROCESSOR 审中-公开
    处理器，其数据处理方法，以及包括处理器的存储器系统

    公开(公告)号：US20120310621A1

    公开(公告)日：2012-12-06

    申请号：US13474942

    申请日：2012-05-18

    申请人： SEH WOONG JEONG ,  Jae Sop Kong

    发明人： SEH WOONG JEONG ,  Jae Sop Kong

    IPC分类号： G06F9/455 ,  G06F12/00

    CPC分类号： G06F13/161 ,  G06F13/105

    摘要： A processor includes an emulator configured to receive an access command from a second memory controller, and a first memory controller configured to control an operation of a memory. The emulator is configured to determine whether the first memory controller is available to perform an operation corresponding to the access command, and transmit a wait signal to the second memory controller upon determining that the first memory controller is not available to perform the operation.

    摘要翻译： 处理器包括被配置为从第二存储器控制器接收访问命令的仿真器和被配置为控制存储器的操作的第一存储器控制器。 仿真器被配置为确定第一存储器控制器是否可用于执行与访问命令相对应的操作，并且在确定第一存储器控制器不可用于执行操作时将等待信号发送到第二存储器控制器。

    3D DISPLAY APPARATUS AND METHODS WITH VIDEO PROCESSING AND FRAME PACKING BASED ON DISPLAY FORMAT INFORMATION
    7.
    发明申请
    3D DISPLAY APPARATUS AND METHODS WITH VIDEO PROCESSING AND FRAME PACKING BASED ON DISPLAY FORMAT INFORMATION 审中-公开
    基于显示格式信息的视频处理和框架包装的3D显示装置和方法

    公开(公告)号：US20120062710A1

    公开(公告)日：2012-03-15

    申请号：US13232435

    申请日：2011-09-14

    申请人： Dong Han Lee ,  Jae Sop Kong

    发明人： Dong Han Lee ,  Jae Sop Kong

    IPC分类号： H04N13/04

    CPC分类号： H04N13/398 ,  H04N13/106 ,  H04N13/139 ,  H04N13/15

    摘要： A 3D display engine includes a timing generator circuit configured to receive format information from a 3D display and to responsively generate display timing information, a video image data processor circuit configured to receive and process left and right video image data, a 3D format generator circuit configured to frame-pack the processed left and right video image data and a controller circuit configured to control the video image data processor circuit and the 3D format generator circuit responsive to the display timing information.

    摘要翻译： 3D显示引擎包括定时发生器电路，其被配置为从3D显示器接收格式信息并且响应地生成显示定时信息，视频图像数据处理器电路被配置为接收和处理左视频图像数据和右视频图像数据; 3D格式发生器电路配置 对经处理的左右视频图像数据进行帧打包，以及控制器电路，被配置为响应于显示定时信息来控制视频图像数据处理器电路和3D格式发生器电路。