Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof
    1.
    发明授权
    Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof 有权
    虚拟接地单晶体管存储单元,并入其的存储器阵列及其操作方法

    公开(公告)号:US06873004B1

    公开(公告)日:2005-03-29

    申请号:US10358645

    申请日:2003-02-04

    摘要: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

    摘要翻译: 不对称的虚拟接地单晶体管浮动栅极存储单元具有覆盖p阱中的沟道区的浮置栅极,位于重掺杂n +漏极区和轻掺杂n-源区之间的沟道区。 称为“卤素”的重掺杂p +区被设置在与重掺杂n +漏极相邻的沟道中。 浮栅通过通常薄的隧道氧化物与沟道区间隔开。 具有渐变源/沟道结的轻掺杂源减少源侧CHE生成。 在一个变型中,源极和浮置栅极之间的较厚的氧化物减少了源极侧的CHE注入。 在与漏极相邻的沟道中具有卤素注入的重掺杂漏极增强漏侧CHE生成。

    Threshold voltage convergence
    2.
    发明授权
    Threshold voltage convergence 有权
    门限电压收敛

    公开(公告)号:US06728140B2

    公开(公告)日:2004-04-27

    申请号:US10011157

    申请日:2001-12-05

    IPC分类号: G11C1604

    CPC分类号: G11C16/3409 G11C16/3404

    摘要: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

    摘要翻译: 收敛信号包括用于在一个或多个快闪EEPROM存储单元(晶体管)中执行收敛过程的一系列电压脉冲。 在一种情况下,会聚信号中的后续电压脉冲各自具有比先前脉冲更高的电压。 在另一种情况下,会聚信号中的后续电压脉冲各自具有比先前脉冲更长的持续时间。 集成电路包括存储单元的阵列和控制将收敛信号应用于一个或多个存储器单元的擦除控制单元。 集成电路可以是使用批量,扇区或页面模式擦除的串行或并行闪存EEPROM。

    Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor
    3.
    发明授权
    Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor 有权
    虚拟地非易失性半导体存储器阵列结构及其集成电路结构

    公开(公告)号:US06826080B2

    公开(公告)日:2004-11-30

    申请号:US10154979

    申请日:2002-05-24

    IPC分类号: G11C1604

    CPC分类号: G11C16/0491 G11C16/08

    摘要: In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

    摘要翻译: 在非易失性存储单元阵列中,每个扇区的存储单元被组织成连续单元组,这些组优选地具有相同的尺寸,并且优选地通过适当的隔离结构(例如场电介质)在行和列方向上彼此隔离 或沟槽电介质。 由于单元组隔离,每组列线可以通过其自己的相对较小的程序列选择进行解码,优选地以所有列列组为基本相同的形式复制。 虽然每个节目列选择优选地用于解码一组列线,但是如果需要解码两组或更多组列线,则可以使用较大的节目列选择。 读列选择可以根据需要对一行或多组列线进行解码。 解码的列线的数量可以与解码的列线的数量相同或不同。