公开(公告)号：US06873004B1

公开(公告)日：2005-03-29

申请号：US10358645

申请日：2003-02-04

申请人： Kyung Joon Han ,  Steve K. Hsia ,  Joo Weon Park ,  Gyu-Wan Kwon ,  Jong Seuk Lee

发明人： Kyung Joon Han ,  Steve K. Hsia ,  Joo Weon Park ,  Gyu-Wan Kwon ,  Jong Seuk Lee

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7885

摘要： An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

摘要翻译： 不对称的虚拟接地单晶体管浮动栅极存储单元具有覆盖p阱中的沟道区的浮置栅极，位于重掺杂n +漏极区和轻掺杂n-源区之间的沟道区。 称为“卤素”的重掺杂p +区被设置在与重掺杂n +漏极相邻的沟道中。 浮栅通过通常薄的隧道氧化物与沟道区间隔开。 具有渐变源/沟道结的轻掺杂源减少源侧CHE生成。 在一个变型中，源极和浮置栅极之间的较厚的氧化物减少了源极侧的CHE注入。 在与漏极相邻的沟道中具有卤素注入的重掺杂漏极增强漏侧CHE生成。

公开(公告)号：US06826080B2

公开(公告)日：2004-11-30

申请号：US10154979

申请日：2002-05-24

申请人： Joo Weon Park ,  Kyung Joon Han ,  Gyu-Wan Kwon ,  Jong Seuk Lee

发明人： Joo Weon Park ,  Kyung Joon Han ,  Gyu-Wan Kwon ,  Jong Seuk Lee

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/08

摘要： In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

摘要翻译： 在非易失性存储单元阵列中，每个扇区的存储单元被组织成连续单元组，这些组优选地具有相同的尺寸，并且优选地通过适当的隔离结构（例如场电介质）在行和列方向上彼此隔离 或沟槽电介质。 由于单元组隔离，每组列线可以通过其自己的相对较小的程序列选择进行解码，优选地以所有列列组为基本相同的形式复制。 虽然每个节目列选择优选地用于解码一组列线，但是如果需要解码两组或更多组列线，则可以使用较大的节目列选择。 读列选择可以根据需要对一行或多组列线进行解码。 解码的列线的数量可以与解码的列线的数量相同或不同。

公开(公告)号：US06728140B2

公开(公告)日：2004-04-27

申请号：US10011157

申请日：2001-12-05

申请人： Kyung Joon Han ,  Joo Weon Park ,  Gyu-Wan Kwon ,  Dung Tran ,  Steve K. Hsia ,  Jong Seuk Lee ,  Dae Hyun Kim

发明人： Kyung Joon Han ,  Joo Weon Park ,  Gyu-Wan Kwon ,  Dung Tran ,  Steve K. Hsia ,  Jong Seuk Lee ,  Dae Hyun Kim

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

摘要翻译： 收敛信号包括用于在一个或多个快闪EEPROM存储单元（晶体管）中执行收敛过程的一系列电压脉冲。 在一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更高的电压。 在另一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更长的持续时间。 集成电路包括存储单元的阵列和控制将收敛信号应用于一个或多个存储器单元的擦除控制单元。 集成电路可以是使用批量，扇区或页面模式擦除的串行或并行闪存EEPROM。

公开(公告)号：US07558900B2

公开(公告)日：2009-07-07

申请号：US11078205

申请日：2005-03-11

申请人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

发明人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/42

CPC分类号： G11C7/1045 ,  G11C8/04 ,  G11C16/26 ,  G11C2207/108 ,  G11C2216/30

摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

摘要翻译： 串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。 在单位串行模式下，数据传输通过引脚逐位传输。 在多位串行模式下，通过各个引脚一次传输多个连续位。 串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装 。 单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率 显着快于标准串行闪存的可用性。

公开(公告)号：US20100049948A1

公开(公告)日：2010-02-25

申请号：US12459590

申请日：2009-07-02

申请人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

发明人： Robin J. Jigour ,  Eungjoon Park ,  Joo Weon Park ,  Jong Seuk Lee

IPC分类号： G06F9/30 ,  G06F12/00 ,  G06F12/02

CPC分类号： G11C7/1045 ,  G11C8/04 ,  G11C16/26 ,  G11C2207/108 ,  G11C2216/30

摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

摘要翻译： 串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。 在单位串行模式下，数据传输通过引脚逐位传输。 在多位串行模式下，通过各个引脚一次传输多个连续位。 串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装 。 单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率 显着快于标准串行闪存的可用性。

公开(公告)号：US06909639B2

公开(公告)日：2005-06-21

申请号：US10421458

申请日：2003-04-22

申请人： Joo Weon Park ,  Poongyeub Lee ,  Eungjoon Park ,  Kyung Joon Han

发明人： Joo Weon Park ,  Poongyeub Lee ,  Eungjoon Park ,  Kyung Joon Han

IPC分类号： G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L29/7885

摘要： The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.

摘要翻译： 通过在编程期间放电非易失性存储器阵列的浮置位线来减少位干扰的问题。 示例性虚拟接地存储器阵列使用使用Fowler-Nordheim（“FN”）隧道，高导电性和长度位线，埋入和相对短的子位线以及用于控制的编程放电电路来编程的单晶体管浮栅型存储器单元 当编程中某些位线悬空时，位线上的杂散电压可能会出现。 分别与位线耦合的放电控制晶体管将电流引入放电部分。 可以为每个位线提供放电部分，或者由所有位线共享放电部分。 放电部分可以是通过编程处理使用的固定电路部分，或者可以从多个放电选项中选择。

公开(公告)号：US06775184B1

公开(公告)日：2004-08-10

申请号：US10349384

申请日：2003-01-21

申请人： Joo Weon Park ,  Poongyeub Lee

发明人： Joo Weon Park ,  Poongyeub Lee

IPC分类号： G11C1400

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A memory integrated circuit includes a nonvolatile memory array that is programmed in page mode. A volatile utility memory is connected to the memory array, and is at least a page in size so that an entire page of data that is either being programmed into or read from the memory array may be stored in the utility memory, thereby providing a single readily accessible and fully functional volatile memory that supports a variety of data operations such as nonvolatile memory programming, program-verify when supplemented with a program verify detector, data compare when supplemented with a comparator, and other operations including, in particular, operations that can benefit from the availability of a fast volatile memory to store an entire page of program data or read data. The outputs of the program verify detector, the comparator, and potentially the other operations circuits are furnished to a memory control circuit for controlling the memory or setting particular register values, or may be furnished as output through an I/O circuit that implements data input/output functions and performs various data routing and buffering functions for the integrated circuit memory.

摘要翻译： 存储器集成电路包括以页模式编程的非易失性存储器阵列。 易失性效用存储器连接到存储器阵列，并且至少是一个页面大小，使得正在被编程到存储器阵列中或从存储器阵列读取的整个数据页可以存储在效用存储器中，从而提供单个 易于访问和全功能的易失性存储器，其支持各种数据操作，例如非易失性存储器编程，补充有程序验证检测器时的程序验证，补充比较器时的数据比较，以及其他操作，特别是可以 受益于快速易失性存储器的可用性，以存储整个程序数据页面或读取数据。 程序验证检测器，比较器和潜在的其他操作电路的输出被提供给用于控制存储器或设置特定寄存器值的存储器控​​制电路，或者可以通过实现数据输入的I / O电路作为输出 /输出功能，并为集成电路存储器执行各种数据路由和缓冲功能。

公开(公告)号：US06768671B1

公开(公告)日：2004-07-27

申请号：US10382719

申请日：2003-03-05

申请人： Poongyeub Lee ,  Joo Weon Park ,  Kwangho Kim ,  Eungjoon Park

发明人： Poongyeub Lee ,  Joo Weon Park ,  Kwangho Kim ,  Eungjoon Park

IPC分类号： G11C1616

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/3418

摘要： In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.

摘要翻译： 在非易失性存储器单元的阵列中，根据需要，甚至整个存储单元阵列可以将多个存储器单元放置在大块的单个区域中，示例性地为p阱。 外设电路用于将存储器阵列有效地划分为块和块组，并且在页或块擦除操作期间在这些块和组内建立合适的偏置和反偏置以限制擦除干扰。 每个组都有自己的一组电压开关，它们为各种工作模式（包括擦除）提供偏置电压。 每个电压开关在选择组时提供大的正电压，或者当其组被选择时提供大的负电压。 该组的尺寸被确定为电压开关所需的擦除干扰程度和衬底面积之间的折衷。

公开(公告)号：US5777922A

公开(公告)日：1998-07-07

申请号：US730873

申请日：1996-10-18

申请人： Young Jung Choi ,  Joo Weon Park

发明人： Young Jung Choi ,  Joo Weon Park

IPC分类号： G11C7/18 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C7/18 ,  G11C16/0491 ,  H01L27/115

摘要： The present invention provides a flash memory device wherein memory cells in each of the memory cell blocks are divided into a plurality of memory cell groups. In each memory cell group, local bit lines are laid out connected by segmentation transistors. When selecting a memory cell, only a local bit line connected to a memory cell selected by an operation of the segmentation transistor is coupled to a global bit line so that the load to be applied to the bit lines is minimized during the read out operation.

摘要翻译： 本发明提供一种闪速存储器件，其中每个存储单元块中的存储单元被分成多个存储单元组。 在每个存储单元组中，局部位线被分割晶体管连接。 当选择存储器单元时，只有连接到通过分割晶体管的操作选择的存储器单元的本地位线被耦合到全局位线，使得在读出操作期间施加到位线的负载被最小化。

公开(公告)号：US5920225A

公开(公告)日：1999-07-06

申请号：US770700

申请日：1996-12-19

申请人： Young Jung Choi ,  Joo Weon Park

发明人： Young Jung Choi ,  Joo Weon Park

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8242 ,  H01L27/108 ,  H02M3/07 ,  G05F3/02

CPC分类号： G05F3/242 ,  G11C16/30 ,  H02M3/073

摘要： The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power supply voltages for the pumping unit block.

摘要翻译： 本发明公开了一种不受根据本发明的负载电容器或电源电压驱动电路的影响的负电压驱动电路，包括交叉抽运电路，泵单元块和用于提供VCC或VSS电源的电路 泵单元块的电压。