Thin film transistor array substrate and method for manufacturing the same
    1.
    发明授权
    Thin film transistor array substrate and method for manufacturing the same 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号:US08815692B2

    公开(公告)日:2014-08-26

    申请号:US13772454

    申请日:2013-02-21

    CPC classification number: H01L33/0041 H01L29/4908 H01L29/66765

    Abstract: A thin film transistor array substrate having excellent characteristics and a method for manufacturing the same are disclosed. The thin film transistor array substrate includes a substrate, a gate electrode positioned on the substrate, a gate insulating layer positioned on the gate electrode, an active layer which is positioned on the gate insulating layer and includes a channel, an ohmic contact layer positioned on the active layer, and a source electrode and a drain electrode which are respectively connected to both sides of the active layer through the ohmic contact layer. The gate insulating layer includes a phosphorus-doped layer positioned adjacent to the active layer.

    Abstract translation: 公开了具有优异特性的薄膜晶体管阵列基板及其制造方法。 所述薄膜晶体管阵列基板包括基板,位于所述基板上的栅电极,位于所述栅电极上的栅极绝缘层,位于所述栅极绝缘层上并包括沟道的有源层,位于所述栅极绝缘层上的欧姆接触层 有源层,以及源电极和漏电极,分别通过欧姆接触层连接到有源层的两侧。 栅极绝缘层包括邻近有源层定位的磷掺杂层。

    THIN-FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE COMPRISING THE SAME
    2.
    发明申请
    THIN-FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE COMPRISING THE SAME 有权
    薄膜晶体管衬底和包含该衬底的显示器件

    公开(公告)号:US20170005152A1

    公开(公告)日:2017-01-05

    申请号:US15197351

    申请日:2016-06-29

    Abstract: A thin-film transistor substrate and a display device comprising the same are provided which can improve display quality by reducing or preventing deterioration of the characteristics of thin-film transistors. The thin-film transistor substrate comprises thin-film transistors on a lower protective metal layer. Each thin-film transistor comprises a buffer layer, a semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a source electrode and a drain electrode, and a first electrode. The lower protective metal layer is electrically connected to the gate electrode and overlaps the channel region of the semiconductor layer.

    Abstract translation: 提供了一种薄膜晶体管基板和包括该薄膜晶体管基板的显示装置,其可以通过减少或防止薄膜晶体管的特性劣化来提高显示质量。 薄膜晶体管衬底包括在下保护金属层上的薄膜晶体管。 每个薄膜晶体管包括缓冲层,半导体层,第一绝缘膜,栅电极,第二绝缘膜,源电极和漏电极以及第一电极。 下保护金属层电连接到栅电极并与半导体层的沟道区重叠。

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