公开(公告)号：US20240005880A1

公开(公告)日：2024-01-04

申请号：US18368230

申请日：2023-09-14

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

CPC classification number: G09G3/3291 ,  G09G2310/08 ,  G09G2310/0278 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20220375417A1

公开(公告)日：2022-11-24

申请号：US17879052

申请日：2022-08-02

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20250095594A1

公开(公告)日：2025-03-20

申请号：US18924260

申请日：2024-10-23

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20210201832A1

公开(公告)日：2021-07-01

申请号：US17137084

申请日：2020-12-29

Applicant: LG Display Co., Ltd.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20210090503A1

公开(公告)日：2021-03-25

申请号：US16897811

申请日：2020-06-10

Applicant: LG Display Co., Ltd.

Inventor： JongHyuck LEE ,  Donghyang LEE

IPC: G09G3/3266 ,  G09G3/3275 ,  G09G3/3233 ,  H01L27/32

Abstract: Provided are a gate driver and a display device. A low-resolution area is disposed in a portion of an active area, and an optical sensor is disposed on a side of the low-resolution area opposite to a surface of the low-resolution area on which an image is displayed, such that the display device displays images on the low-resolution area and performs sensing using the optical sensor. The low-resolution area and a high-resolution area surrounding the low-resolution area are driven using different gate lines. Image compensation for the low-resolution area is easily performed to reduce or remove the difference in the image quality between the low-resolution area and the surrounding areas.