公开(公告)号：US20240005880A1

公开(公告)日：2024-01-04

申请号：US18368230

申请日：2023-09-14

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

CPC classification number: G09G3/3291 ,  G09G2310/08 ,  G09G2310/0278 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20180167070A1

公开(公告)日：2018-06-14

申请号：US15824667

申请日：2017-11-28

Applicant: LG DISPLAY CO., LTD.

Inventor： Nakwoo KIM

IPC: H03K19/017 ,  G02F1/1362 ,  G09G3/36

CPC classification number: H03K19/01742 ,  G02F1/136286 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  H01L27/1214 ,  H03K19/017

Abstract: Agate driver includes a shift register including a plurality of stages. The nth stage among the stages includes a buffer switching element having a gate electrode connected to a Q-node and a drain electrode to receive a first clock, a first switching element having a gate electrode to receive a second clock and a drain electrode to receive a start pulse, and a second switching element having a gate electrode to receive the second clock and a drain electrode to receive a gate high voltage, a first capacitor connected between the Q-node and a source electrode of the buffer switching element, and a second capacitor connected between the drain electrode of the first switching element and the Q-node. The number of switching elements included in the gate driver is drastically reduced, such that the numbers of clock signals and voltage signals required for driving the gate driver can be reduced.

公开(公告)号：US20220375417A1

公开(公告)日：2022-11-24

申请号：US17879052

申请日：2022-08-02

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20170154944A1

公开(公告)日：2017-06-01

申请号：US15299364

申请日：2016-10-20

Applicant: LG Display Co., Ltd.

Inventor： Nakwoo KIM ,  Jaeho SIM ,  Donghyun YEO

IPC: H01L27/32

CPC classification number: H01L27/3276 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3225 ,  H01L27/3272

Abstract: An organic light emitting display in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode, includes the gate electrode of the driving thin film transistor; a signal line adjacent to the gate electrode of the driving thin film transistor; and a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer therebetween, wherein the first shielding electrode extends further towards the signal line than the gate electrode of the driving thin film transistor.

公开(公告)号：US20250095594A1

公开(公告)日：2025-03-20

申请号：US18924260

申请日：2024-10-23

Applicant: LG DISPLAY CO., LTD.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.

公开(公告)号：US20210201832A1

公开(公告)日：2021-07-01

申请号：US17137084

申请日：2020-12-29

Applicant: LG Display Co., Ltd.

Inventor： Sanghyun LIM ,  Nakwoo KIM ,  Donghyang LEE

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A gate driving circuit includes a Q node controller generating a voltage of a Q node by using a first clock, a second clock, a third clock, and a start signal; a QB node controller generating a voltage of a QB node by using the second clock and the third clock; and an output part including a pull-up TFT and a pull-down TFT and generating an output signal including a first pulse interval, of a gate-on voltage, synchronized with a part of the first clock according to the voltages of the Q node and the QB node.