公开(公告)号：US10783820B2

公开(公告)日：2020-09-22

申请号：US16136683

申请日：2018-09-20

Applicant: LG Display Co., Ltd.

Inventor： Seok Noh ,  Hae-Jin Park ,  Ki-Min Son

IPC: G09G3/36 ,  G09G3/20 ,  H03K17/687 ,  G09G3/3266 ,  G11C19/28 ,  H03K17/16

Abstract: Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller.

公开(公告)号：US11282428B2

公开(公告)日：2022-03-22

申请号：US17013191

申请日：2020-09-04

Applicant: LG Display Co., Ltd.

Inventor： In-Hyo Han ,  Ki-Min Son ,  Kil-Hwan Oh ,  Hae-Jin Park ,  Kyung-Min Kim

IPC: G09G3/20 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233 ,  H01L51/52 ,  H01L27/02 ,  G09G3/3225 ,  H01L27/12

Abstract: The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

公开(公告)号：US10957755B2

公开(公告)日：2021-03-23

申请号：US15809806

申请日：2017-11-10

Applicant: LG Display Co., Ltd.

Inventor： In-Hyo Han ,  Ki-Min Son ,  Kil-Hwan Oh ,  Hae-Jin Park ,  Kyung-Min Kim

IPC: G09G5/10 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233 ,  H01L51/52 ,  H01L27/02 ,  G09G3/3225 ,  G09G3/20 ,  H01L27/12

Abstract: A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.