公开(公告)号：US09911376B2

公开(公告)日：2018-03-06

申请号：US15134157

申请日：2016-04-20

Applicant: LG Display Co., Ltd.

Inventor： HwaYoung Kim ,  MyungKook Moon

IPC: G09G5/39 ,  G09G3/20 ,  G09G3/36

CPC classification number: G09G3/2096 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0254 ,  G09G2310/08 ,  G09G2330/028

Abstract: A display device including plural timing controllers is provided. The display device includes a display panel, first and second data drive circuits, first and second timing controllers. The display panel includes pixels and data lines. The first data drive circuit supplies data voltages to a part of the data lines. The second data drive circuit supplies data voltages to the other of the data lines. The first and second timing controllers controls the display panel according to a first inversion scheme when images displayed by first and second image data do not include predetermined problem patterns, and controls the display panel according to an inversion scheme other than the first inversion scheme when the images displayed by the first and second image data include at least one of the predetermined problem patterns.

公开(公告)号：US10056024B2

公开(公告)日：2018-08-21

申请号：US15136804

申请日：2016-04-22

Applicant: LG Display Co., Ltd.

Inventor： HwaYoung Kim ,  ByungMu Jung ,  SangSoo Han ,  SungJoon Moon

IPC: G09G3/20 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/36

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/061 ,  G09G2310/08 ,  H01L27/3276

Abstract: A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.