Abstract:
A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.
Abstract:
A liquid crystal display device discharges residual charge within the liquid crystal display panel. The liquid crystal display device comprises pixels defined by gate lines and data lines intersecting with each other and switching elements for driving the plurality of pixels; a level shifter comprising a first transistor connected between a gate-on voltage terminal and an output terminal and a second transistor connected between a gate-off voltage terminal and the output terminal to selectively output either the gate-on voltage or gate-off voltage to the plurality of gate lines; and a discharge circuit forming a discharge path connecting the gate-off voltage terminal and the ground terminal. The second transistor is turned on during the power-on of the liquid crystal display panel to apply the gate-off voltage. The discharge circuit is turned on to discharge the residual charge of the liquid crystal display panel through the discharge path.