公开(公告)号：US20210201767A1

公开(公告)日：2021-07-01

申请号：US17129412

申请日：2020-12-21

Applicant: LG Display Co., Ltd.

Inventor： JaeKyu PARK ,  SooHong CHOI ,  HongJae SHIN ,  Seongho YUN ,  Jeongrim SEO

IPC: G09G3/32

Abstract: A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.

公开(公告)号：US20240290277A1

公开(公告)日：2024-08-29

申请号：US18442957

申请日：2024-02-15

Applicant: LG Display Co., Ltd.

Inventor： Jeongrim SEO ,  SooHong CHOI ,  HongJae SHIN

IPC: G09G3/3266 ,  G09G3/32

CPC classification number: G09G3/3266 ,  G09G3/32 ,  G09G2300/0439 ,  G09G2310/0267 ,  G09G2310/0291 ,  G09G2310/061 ,  G09G2310/08

Abstract: The present disclosure relate to a gate driving panel circuit, a display panel and a display device that are capable of stably supplying high voltages and low voltages by disposing the gate driving panel circuit in a display panel and applying a stable power wiring structure.

公开(公告)号：US20220208109A1

公开(公告)日：2022-06-30

申请号：US17553368

申请日：2021-12-16

Applicant: LG Display Co., Ltd.

Inventor： Jeongrim SEO

IPC: G09G3/3266 ,  G09G3/3291

Abstract: A gate driver circuit can include a plurality of stage circuits, in which each of the plurality of stage circuits supplies a gate signal to gate lines arranged in a display panel, and includes an M node, a Q node, a QH node, a QB node, a line selector, a Q node controller, a Q node and QH node stabilizer, an inverter, a QB node stabilizer, a carry signal output circuit portion, a gate signal output circuit portion, and a Q node bootstrapper, in which the Q node bootstrapper is connected between the carry signal output circuit portion and the gate signal output circuit portion, or the gate signal output circuit portion is connected between the carry signal output circuit portion and the Q node bootstrapper.