公开(公告)号：US20210201767A1

公开(公告)日：2021-07-01

申请号：US17129412

申请日：2020-12-21

Applicant: LG Display Co., Ltd.

Inventor： JaeKyu PARK ,  SooHong CHOI ,  HongJae SHIN ,  Seongho YUN ,  Jeongrim SEO

IPC: G09G3/32

Abstract: A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.

公开(公告)号：US20240290251A1

公开(公告)日：2024-08-29

申请号：US18442945

申请日：2024-02-15

Applicant: LG Display Co., Ltd.

Inventor： Seongho YUN ,  HongJae SHIN ,  YongHo KIM

IPC: G09G3/32 ,  G09G3/3266

CPC classification number: G09G3/32 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/045 ,  G09G2330/021

Abstract: The present disclosure relates to a display panel for gate driving and a display device, which include a gate driving panel circuit and are capable of providing a stable power wiring structure for stably supplying high voltages and low voltages to the gate driving panel circuit disposed in the display panel.

公开(公告)号：US20240395216A1

公开(公告)日：2024-11-28

申请号：US18790899

申请日：2024-07-31

Applicant: LG Display Co., Ltd.

Inventor： Jaeyi CHOI ,  Seongho YUN ,  SooHong CHOI

IPC: G09G3/3266 ,  G09G3/3291

Abstract: The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.

公开(公告)号：US20230215378A1

公开(公告)日：2023-07-06

申请号：US18054872

申请日：2022-11-11

Applicant: LG Display Co., Ltd.

Inventor： Jaeyi CHOI ,  Seongho YUN ,  SooHong CHOI

IPC: G09G3/3266 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/3291 ,  G09G2310/08 ,  G09G2310/0278

Abstract: The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.

公开(公告)号：US20220199034A1

公开(公告)日：2022-06-23

申请号：US17553406

申请日：2021-12-16

Applicant: LG Display Co., Ltd.

Inventor： Seongho YUN ,  Dongmyoung KIM

IPC: G09G3/3266

Abstract: A gate driver circuit can include a plurality of stage circuits, in which each of the plurality of stage circuits supplies a gate signal to gate lines arranged in a display panel, and includes an M node, a Q1 node, a Q2 node, a QB node, a line selector, a Q1 node controller, a Q1 node stabilizer, an inverter, a QB node stabilizer, a carry signal output circuit portion, and a gate signal output circuit portion, in which a first low-potential voltage level, a third low-potential voltage level, and a fourth low-potential voltage level for operating the gate driver circuit are set to different values, and the gate driver circuit can have a reduced size and better prevent leakage current while also providing more stable gate signals.