Abstract:
A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.
Abstract:
A display panel and a display device which may remove load deviation between clock signal lines. More specifically, the display device includes a substrate including a display area capable of displaying an image and a non-display area disposed around the display area, the display area including a subpixel and a gate line for driving the subpixel; a gate driving panel circuit disposed in the non-display area and configured to output a gate signal to the gate line; a plurality of clock signal lines disposed in the non-display area and positioned to be farther from the display area than the gate driving panel circuit to supply a plurality of clock signals to the gate driving panel circuit; an overcoat layer disposed on the plurality of clock signal lines and the gate driving panel circuit; and a light emitting element included in the subpixel, comprising a cathode electrode disposed on the overcoat layer and extending from the display area to the non-display area, wherein the cathode electrode is disposed not to overlap the plurality of clock signal lines.
Abstract:
The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.
Abstract:
The present disclosure relates to a display panel and a display device that have a pad structure including a defect detection pad and configured to be suitable for a structure in which a gate driving panel circuit is disposed. The display panel and the display device provide advantages of detecting in advance a possibility that a defect accident may occur in the display panel and preventing such a defect accident in the display panel.
Abstract:
The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.
Abstract:
Embodiments of the disclosure relate to a display panel and a display device and, specifically, may provide a display panel comprising a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, a plurality of gate high-potential voltage lines which are disposed in a side of the gate driving circuit for transferring a plurality of gate high-potential voltages, a plurality of gate low-potential voltage lines which are disposed in other side of the gate driving circuit for transferring a plurality of gate low-potential voltages, and a plurality of gate low-potential voltage connection lines which are extended through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit.
Abstract:
The present disclosure relate to a gate driving panel circuit, a display panel and a display device that are capable of stably supplying high voltages and low voltages by disposing the gate driving panel circuit in a display panel and applying a stable power wiring structure.
Abstract:
By forming a repair structure in a horizontal direction and vertical direction by using one or more repair lines between two or more pixels adjacent to each other in a display panel, even though a dark spot appears due to a defective operation of one pixel, the one pixel may be compensated to be driven by using the other pixel.
Abstract:
An organic light emitting display device and a method of repairing the device are discussed. According to an embodiment, the device includes a display panel having pixels, each including an OLED in every pixel area defined as scan and data lines intersect with each other and having a repair structure in at least one of horizontal and vertical directions between adjacent pixels by one or more repair lines; a timing controller configured to generate compensation data when a dark spot is generated in one of the plurality of pixels of the display panel, and adjust a magnitude of image data according to the compensation data; and a data driver configured to adjust a magnitude of a data voltage according to the image data adjusted in magnitude, and output the data voltage adjusted in magnitude to the data lines.