公开(公告)号：US20240105122A1

公开(公告)日：2024-03-28

申请号：US18531453

申请日：2023-12-06

Applicant: LG Display Co., Ltd.

Inventor： Ki Min SON ,  Chang Hee KIM ,  Seok NOH

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2330/021

Abstract: A pixel circuit comprises a first switch element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which a initialization pulse is applied, and a second electrode connected to a second node; a second switch element comprising a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switch element comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switch element comprising a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node.

公开(公告)号：US20230010792A1

公开(公告)日：2023-01-12

申请号：US17848175

申请日：2022-06-23

Applicant: LG DISPLAY CO., LTD.

Inventor： Seung Ho HEO ,  Dong Hyun LEE ,  Seok NOH ,  Ki Min SON ,  Hun Ki SHIN

IPC: G09G3/3266 ,  G09G3/3233

Abstract: Provided are a gate driving circuit and a display device including the same. The gate driving circuit includes a first controller configured to control a first control node to act as a pull-up control node to turn on a first transistor when an activation clock is input to the first controller for a first unit time, and to be deactivated when a deactivation clock is input thereto for a second unit time; and a second controller configured to control a second control node to act as a pull-up control node to turn on a second transistor when the activation clock is input to the second controller for the second unit time, and to be deactivated when the deactivation clock is input thereto for the first unit time.

公开(公告)号：US20230009494A1

公开(公告)日：2023-01-12

申请号：US17860085

申请日：2022-07-07

Applicant: LG Display Co., Ltd.

Inventor： Seok NOH ,  Ki Min SON

IPC: G09G3/3266 ,  G09G3/3233

Abstract: Disclosed are a gate driver and a display panel including the same. The gate driver according to an embodiment includes a plurality of signal transfer units cascade-connected via a carry line to which a carry signal is applied from a previous signal transfer unit, and an nth (n is a positive integer) signal transfer unit includes a first output unit configured to output a first gate signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a second control node configured to pull down the output voltage; and a second output unit configured to output a second gate signal in which a phase of the first gate signal is reversed to a second output node, wherein the second output unit may include a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of an (n-i)th (i is a positive integer less than n) signal transfer unit; and a second pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j)th (j is a natural number greater than n) signal transfer unit.

公开(公告)号：US20180144711A1

公开(公告)日：2018-05-24

申请号：US15812896

申请日：2017-11-14

Applicant: LG Display Co., Ltd.

Inventor： Seok NOH ,  Injune KIM ,  Kimin SON

IPC: G09G3/36

Abstract: A display device comprises: a pixel array including pixels connected to gate lines; a gate driver that sequentially supplies scan signals to the gate lines by using a plurality of stages connected in cascade; and a driving voltage generator that supplies first and second driving voltages to the gate driver and inverts the first and second driving voltages of opposite phases at given intervals, wherein an nth stage (n is a natural number), among the stages of the gate driver, comprises: a start controller that charges a Q1 node in a period when an (n−1)th scan signal and a first clock signal are synchronized, and charges a Q1B node in a period when an (n−1)th carry signal, opposite in phase to the (n−1)th scan signal, and the first clock signal are synchronized; a first node controller that charges a Q2 node or a Q2B node in response to a voltage at the Q1 node; a first output control transistor that outputs an nth scan signal through a Q node in response to a voltage at the Q2 node; and a second output control transistor that charges the Q node with the second driving voltage in response to a voltage at the Q2B node.

公开(公告)号：US20190103049A1

公开(公告)日：2019-04-04

申请号：US16136683

申请日：2018-09-20

Applicant: LG Display Co., Ltd.

Inventor： Seok NOH ,  Hae-Jin PARK ,  Ki-Min SON

IPC: G09G3/20 ,  H03K17/687 ,  G09G3/3266 ,  G09G3/36

Abstract: Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller.

公开(公告)号：US20190043405A1

公开(公告)日：2019-02-07

申请号：US16044260

申请日：2018-07-24

Applicant: LG Display Co., Ltd.

Inventor： Seok NOH ,  In-Hyo HAN

IPC: G09G3/20

Abstract: Disclosed herein are a gate driver including at least two output buffers to drive at least two gate lines and capable of reducing an output deviation of each output buffer, and a flat panel display device including the same. The gate driver includes a plurality of gate-in-panels (GIPs) for sequentially supplying scan signals to a plurality of gate lines. Each GIP includes one carry signal output unit and at least two scan signal output units to drive at least two gate lines, and the carry signal output unit includes a pull-up transistor controlled by a voltage of a first node, a pull-down transistor controlled by a voltage of a second node, and a boosting capacitor formed between gate and source electrodes of the pull-up transistor.

公开(公告)号：US20170193917A1

公开(公告)日：2017-07-06

申请号：US15391188

申请日：2016-12-27

Applicant: LG DISPLAY CO., LTD.

Inventor： Seok NOH ,  InHyo HAN

IPC: G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/3677 ,  G09G2300/0439 ,  G09G2300/0871 ,  G09G2310/0267 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2320/0223

Abstract: A gate driving module and a gate-in-panel comprising a first pull-up TFT having a terminal connected to a gate driving signal generator and another terminal connected to an end of a first gate line, a first pull-down TFT having a terminal connected to the end of the first gate line and another terminal connected to a low-level voltage terminal, and a second pull-up TFT having a terminal connected to the gate driving signal generator and another terminal connected to another end opposite to the end of the first gate line, wherein the first pull-down TFT is turned off when the first pull-up TFT and the second pull-up TFT are turned on, and the first pull-down TFT is turned on when the first pull-up TFT and the second pull-up TFT are turned off.

公开(公告)号：US20230071094A1

公开(公告)日：2023-03-09

申请号：US17901516

申请日：2022-09-01

Applicant: LG Display Co., Ltd.

Inventor： Ki Min SON ,  Seok NOH ,  Ki Bok PARK ,  Ye Won HONG

IPC: H01L27/32 ,  G11C19/28 ,  G09G3/20 ,  G09G3/3266

Abstract: A display panel and an electronic device including the same are disclosed. A circuit layer of the display panel includes at least a first transistor and a second transistor. The first transistor includes a first oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the first oxide semiconductor pattern, a second electrode in contact with the other side of the first oxide semiconductor pattern, and a first-first metal pattern disposed on the substrate to overlap the first oxide semiconductor pattern. The second transistor includes a second oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the second oxide semiconductor pattern, a second electrode in contact with the other side of the second oxide semiconductor pattern, a first-second metal pattern disposed on the substrate to overlap the second oxide semiconductor pattern, and a second metal pattern disposed between the second oxide semiconductor pattern and the first-second metal pattern.

公开(公告)号：US20230008896A1

公开(公告)日：2023-01-12

申请号：US17859947

申请日：2022-07-07

Applicant: LG Display Co., Ltd.

Inventor： Seok NOH ,  Ki Min SON

IPC: G09G3/3266 ,  G09G3/3233

Abstract: An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.

公开(公告)号：US20200074933A1

公开(公告)日：2020-03-05

申请号：US16548761

申请日：2019-08-22

Applicant: LG Display Co., Ltd.

Inventor： Myungho BAN ,  Inhyo HAN ,  Seok NOH ,  Kimin SON

IPC: G09G3/3266 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3283 ,  G09G3/3291

Abstract: A gate driver includes a gate shift register in which an A block and a B block each having a plurality of stages, the A block and the B block being alternately arranged; scan clock lines inputting a first scan clock group and a second scan clock group each including both image data writing (IDW) scan clocks synchronized with an image write timing and black data insertion (BDI) scan clocks synchronized with a black write timing to the A block and the B block; and carry clock lines inputting carry clocks to the A block and the B block and sense clock lines inputting sense clocks to the A block and the B block, wherein each of the stages belonging to the A block and the B block includes a BDI memory storing a BDI carry signal for outputting the BDI scan clocks.