Abstract:
The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.
Abstract:
By forming a repair structure in a horizontal direction and vertical direction by using one or more repair lines between two or more pixels adjacent to each other in a display panel, even though a dark spot appears due to a defective operation of one pixel, the one pixel may be compensated to be driven by using the other pixel.
Abstract:
A gate driving circuit and a light emitting display apparatus comprising the same are discussed, in which a charging characteristic of a control node is improved. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes first to third control nodes, a node control circuit controlling a voltage of each of the first to third control nodes, and an output buffer circuit outputting each of a scan signal, a sense signal and a carry signal in accordance with each of the first to third control nodes, the node control circuit including a node setup circuit charging a first gate high potential voltage in the first control node in response to a first carry signal supplied from a front stage circuit.
Abstract:
Provided are an organic light emitting display (OLED) device and a method of manufacturing the same. The OLED device includes: an array substrate, an intermediate layer over the array substrate, an insulating layer over the intermediate layer, and a plurality of driving signal lines over the insulating layer in a non-display area of the array substrate, the plurality of driving signal lines being completely separated from the intermediate layer by the insulating layer, each of the plurality of driving signal lines being configured to supply a driving signal from a driving circuit unit to a respective sub-pixel of a pixel among a plurality of pixels, wherein the intermediate layer under the plurality of driving signal lines is configured to reduce visibility of the driving signal lines such that incident light on the intermediate layer is uniformly reflected or absorbed with the plurality of driving signal lines.
Abstract:
The present disclosure relates to a display panel and a display device, and can provide a display panel and a display device that have a clock signal line arrangement structure that is advantageous to electrostatic discharge.
Abstract:
The present disclosure relates to a display panel and a display device, and can provide a display panel and a display device that have a clock signal line arrangement structure that is advantageous to electrostatic discharge.
Abstract:
The present disclosure relates to a display panel and a display device, and can provide a display panel and a display device that have a clock signal line arrangement structure that is advantageous to electrostatic discharge.
Abstract:
A display panel comprising a display area including a plurality of subpixels, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and a plurality of gate high-potential voltage lines which are disposed in the non-display area for transferring a plurality of gate high-potential voltages to the gate driving circuit, wherein plurality of gate high-potential voltage lines include a first gate high-potential voltage line transferring a first gate high-potential voltage for charging a first node of the gate driving circuit, a second gate high-potential voltage line transferring a second gate high-potential voltage for charging a second node of the gate driving circuit, and a third gate high-potential voltage line which is branched from the first gate high-potential voltage line for transferring a third gate high-potential voltage to stabilize a transistor controlling the first node.
Abstract:
An organic light emitting display device and a method of repairing the device are discussed. According to an embodiment, the device includes a display panel having pixels, each including an OLED in every pixel area defined as scan and data lines intersect with each other and having a repair structure in at least one of horizontal and vertical directions between adjacent pixels by one or more repair lines; a timing controller configured to generate compensation data when a dark spot is generated in one of the plurality of pixels of the display panel, and adjust a magnitude of image data according to the compensation data; and a data driver configured to adjust a magnitude of a data voltage according to the image data adjusted in magnitude, and output the data voltage adjusted in magnitude to the data lines.
Abstract:
Provided are an organic light emitting display (OLED) device and a method of repairing the same. The OLED device includes: a first pixel including: a first thin-film transistor (TFT) including a source electrode, a second TFT, and a third TFT including a top gate electrode, a second pixel including an OLED including a first electrode, a repair line extending over: the first electrode of the OLED of the second pixel, the source electrode of the first TFT of the first pixel, and the top gate electrode of the third TFT of the first pixel, an insulating layer between at least a portion of: the top gate electrode of the third TFT of the first pixel, and the repair line.