公开(公告)号：US20210225976A1

公开(公告)日：2021-07-22

申请号：US17220523

申请日：2021-04-01

申请人： LG Display Co., Ltd.

发明人： Tae-Won LEE ,  Jong-Chan PARK ,  Hyun-Chul UM

IPC分类号： H01L27/32 ,  H01L51/52 ,  H01L51/10 ,  H01L27/12

摘要： Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

公开(公告)号：US20200083307A1

公开(公告)日：2020-03-12

申请号：US16533698

申请日：2019-08-06

申请人： LG Display Co., Ltd.

发明人： Tae-Won LEE ,  Jong-Chan PARK ,  Hyun-Chul UM

IPC分类号： H01L27/32 ,  H01L27/12 ,  H01L51/10 ,  H01L51/52

摘要： Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

公开(公告)号：US20230354645A1

公开(公告)日：2023-11-02

申请号：US18218498

申请日：2023-07-05

申请人： LG Display Co., Ltd.

发明人： Tae-Won LEE ,  Jong-Chan PARK ,  Hyun-Chul UM

IPC分类号： H10K59/121 ,  H01L27/12 ,  H10K10/84 ,  H10K50/84

CPC分类号： H10K59/1213 ,  H01L27/1214 ,  H10K10/84 ,  H10K50/84

摘要： Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.