Display Device
    7.
    发明公开
    Display Device 审中-公开

    公开(公告)号:US20230354645A1

    公开(公告)日:2023-11-02

    申请号:US18218498

    申请日:2023-07-05

    摘要: Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

    UTILIZING MONOLAYER MOLECULAR CRYSTALS TO IMPROVE CONTACT PROPERTIES OF ORGANIC FIELD-EFFECT TRANSISTORS

    公开(公告)号:US20230269995A1

    公开(公告)日:2023-08-24

    申请号:US18004135

    申请日:2021-07-07

    IPC分类号: H10K71/15 H10K71/60 H10K10/46

    摘要: A method for manufacturing a semiconductor device having an organic semiconductor material is provided. The method includes performing a large-area solution shearing step to form a monolayer (1L) or bi-layer (2L) C10-DNTT crystals with low shearing speed and forming Au electrodes by thermal evaporation on a wafer. The large-area solution shearing step is performed at a temperature in a range between about 60° C. and about 65° C. and with a shearing speed in a range between about 2 μm/sand about 3 μm/s. The 1L or 2L crystals have single-crystalline domains extending over several millimeters. An organic field-effect transistor (OFET) comprising an active layer that comprises a monolayer (1L) or bi-layer (2L) C10-DNTT crystals formed according to the method is also provided.

    Display device
    10.
    发明授权

    公开(公告)号:US11737317B2

    公开(公告)日:2023-08-22

    申请号:US17220523

    申请日:2021-04-01

    摘要: Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.