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1.发明申请ARRAY SUBSTRATE HAVING INTEGRATED GATE DRIVER AND METHOD OF FABRICATING THE SAME 有权具有集成门驱动器的阵列基板及其制造方法公开(公告)号：US20160035749A1
公开(公告)日：2016-02-04
申请号：US14584918
申请日：2014-12-29
Applicant: LG Display Co., Ltd.
Inventor： In Kang , Tae-Yong Jung , Tae-Keun Lee
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/124 , G02F1/13454 , G09G3/3677 , G09G2300/0408 , H01L27/1248 , H01L27/1259 , H01L29/66765 , H01L29/78669
Abstract: An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.
Abstract translation: 阵列基板包括：基板; 栅极电路区域中的衬底上的栅极连接线; 栅极连接线上的栅极绝缘层; 栅极绝缘层上的有源图案; 源连接线和顺序设置在有源图案上的像素图案; 顺序地设置在所述栅绝缘层上的层间绝缘层和有机图案; 有机图案上的第一钝化层; 以及在所述第一钝化层上的导电图案，所述导电图案耦合到所述栅极连接线和所述像素图案。
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2.发明授权Array substrate having integrated gate driver and method of fabricating the same 有权具有集成栅极驱动器的阵列衬底及其制造方法公开(公告)号：US09583511B2
公开(公告)日：2017-02-28
申请号：US14584918
申请日：2014-12-29
Applicant: LG Display Co., Ltd.
Inventor： In Kang , Tae-Yong Jung , Tae-Keun Lee
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/124 , G02F1/13454 , G09G3/3677 , G09G2300/0408 , H01L27/1248 , H01L27/1259 , H01L29/66765 , H01L29/78669
Abstract: An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.
Abstract translation: 阵列基板包括：基板; 栅极电路区域中的衬底上的栅极连接线; 栅极连接线上的栅极绝缘层; 栅极绝缘层上的有源图案; 源连接线和顺序设置在有源图案上的像素图案; 顺序地设置在所述栅绝缘层上的层间绝缘层和有机图案; 有机图案上的第一钝化层; 以及在所述第一钝化层上的导电图案，所述导电图案耦合到所述栅极连接线和所述像素图案。
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