Gate driver and organic light emitting display device including the same

    公开(公告)号:US12230213B2

    公开(公告)日:2025-02-18

    申请号:US18470890

    申请日:2023-09-20

    Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

    Array substrate having integrated gate driver and method of fabricating the same
    3.
    发明授权
    Array substrate having integrated gate driver and method of fabricating the same 有权
    具有集成栅极驱动器的阵列衬底及其制造方法

    公开(公告)号:US09583511B2

    公开(公告)日:2017-02-28

    申请号:US14584918

    申请日:2014-12-29

    Abstract: An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.

    Abstract translation: 阵列基板包括:基板; 栅极电路区域中的衬底上的栅极连接线; 栅极连接线上的栅极绝缘层; 栅极绝缘层上的有源图案; 源连接线和顺序设置在有源图案上的像素图案; 顺序地设置在所述栅绝缘层上的层间绝缘层和有机图案; 有机图案上的第一钝化层; 以及在所述第一钝化层上的导电图案,所述导电图案耦合到所述栅极连接线和所述像素图案。

    Gate driver and organic light emitting display device including the same

    公开(公告)号:US11367397B2

    公开(公告)日:2022-06-21

    申请号:US17126575

    申请日:2020-12-18

    Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

    Gate Driver and Organic Light Emitting Display Device Including the Same

    公开(公告)号:US20250148990A1

    公开(公告)日:2025-05-08

    申请号:US19019269

    申请日:2025-01-13

    Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

    Light emitting diode display apparatus

    公开(公告)号:US12069904B2

    公开(公告)日:2024-08-20

    申请号:US17559822

    申请日:2021-12-22

    CPC classification number: H10K59/123 H10K59/1213 H01L27/124

    Abstract: A light emitting diode display apparatus includes: a substrate; a driving element region which is formed on the substrate and in which a plurality of driving elements are arranged in a matrix form; and an emitting element region in which a plurality of emitting elements are arranged in a matrix form, wherein the emitting element includes a first electrode which corresponds to each driving element and is electrically connected to each driving element, a second electrode corresponding to the first electrode, and an emitting layer located between the first electrode and the second electrode, wherein an area of the emitting element region is greater than an area of the driving element region.

    Gate driving circuit and display device using the same

    公开(公告)号:US10991302B1

    公开(公告)日:2021-04-27

    申请号:US16918882

    申请日:2020-07-01

    Abstract: A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including at least one n-type transistor and at least one p-type transistor and arranged in the display area, and a gate driving circuit included in the non-display area and outputting a first scan signal for applying a data voltage to driving transistors of the pixel circuits for an initialization time and a second scan signal that represents a same logic voltage as the first scan signal for the initialization time and represents a logic voltage reverse to the first scan signal for a sampling time. A first scan signal generator and a second scan signal generator are integrated using nodes Q/QB of a logic circuit to reduce a bezel size.

    In-cell touch type liquid crystal display device
    9.
    发明授权
    In-cell touch type liquid crystal display device 有权
    电池内触摸式液晶显示装置

    公开(公告)号:US09329424B2

    公开(公告)日:2016-05-03

    申请号:US14584020

    申请日:2014-12-29

    Abstract: An in-cell touch type liquid crystal display device includes a touch line and a dummy touch line along a direction between neighboring pixel electrodes on a first passivation layer; a second passivation layer on the touch line and the dummy touch line; and common electrodes separated from one another in respective touch blocks, and each including first openings corresponding to each pixel region and a second opening corresponding to the touch line, wherein a connection pattern extending over a gate line from a side of the touch line at an inner region of the touch block is connected to a common electrode through a touch contact hole, and wherein an open portion is between the touch line and the dummy touch line.

    Abstract translation: 电池内触摸型液晶显示装置包括沿着第一钝化层上的相邻像素电极之间的方向的触摸线和虚拟触摸线; 在触摸线和虚拟触摸线上的第二钝化层; 以及在相应的触摸块中彼此分离的公共电极,并且每个电极包括对应于每个像素区域的第一开口和对应于触摸线的第二开口,其中,在触摸线的一侧在栅极线上延伸的连接图案 触摸块的内部区域通过触摸接触孔连接到公共电极,并且其中开口部分在触摸线和虚拟触摸线之间。

    ARRAY SUBSTRATE HAVING INTEGRATED GATE DRIVER AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    ARRAY SUBSTRATE HAVING INTEGRATED GATE DRIVER AND METHOD OF FABRICATING THE SAME 有权
    具有集成门驱动器的阵列基板及其制造方法

    公开(公告)号:US20160035749A1

    公开(公告)日:2016-02-04

    申请号:US14584918

    申请日:2014-12-29

    Abstract: An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern.

    Abstract translation: 阵列基板包括:基板; 栅极电路区域中的衬底上的栅极连接线; 栅极连接线上的栅极绝缘层; 栅极绝缘层上的有源图案; 源连接线和顺序设置在有源图案上的像素图案; 顺序地设置在所述栅绝缘层上的层间绝缘层和有机图案; 有机图案上的第一钝化层; 以及在所述第一钝化层上的导电图案,所述导电图案耦合到所述栅极连接线和所述像素图案。

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