公开(公告)号：US20150210919A1

公开(公告)日：2015-07-30

申请号：US14607232

申请日：2015-01-28

Applicant: LG INNOTEK CO. LTD.

Inventor： Ju Yeon WON ,  Jin Gyeong Park ,  In Jae Lee ,  Sung Hoon Kim ,  Won Jin Kim ,  Eui Yeol Yang

IPC: C09K11/02 ,  C03C8/08 ,  C03C3/066 ,  C03C8/04

CPC classification number: C09K11/02 ,  C03C3/066 ,  C03C8/04 ,  C03C8/08 ,  C03C14/006 ,  C03C2204/00 ,  C03C2209/00 ,  C03C2214/16 ,  C09K11/08 ,  H01L33/501 ,  H01L33/505 ,  H01L33/507

Abstract: Provided are a ternary glass composition containing SiO2, B2O3 and ZnO, and a ceramic phosphor plate including a glass frit obtained by vitrification of the glass composition as a matrix and obtained by sintering at least one phosphor.

Abstract translation: 提供含有SiO 2，B 2 O 3和ZnO的三元玻璃组合物，以及包含通过玻璃化玻璃化获得的玻璃料作为基质并通过烧结至少一种荧光体获得的陶瓷荧光体板。

公开(公告)号：US09840663B2

公开(公告)日：2017-12-12

申请号：US14607232

申请日：2015-01-28

Applicant: LG INNOTEK CO., LTD.

Inventor： Ju Yeon Won ,  Jin Gyeong Park ,  In Jae Lee ,  Sung Hoon Kim ,  Won Jin Kim ,  Eui Yeol Yang

IPC: C03C8/08 ,  C03C3/066 ,  C09K11/02 ,  C03C8/04 ,  H01L33/50 ,  C03C14/00

CPC classification number: C09K11/02 ,  C03C3/066 ,  C03C8/04 ,  C03C8/08 ,  C03C14/006 ,  C03C2204/00 ,  C03C2209/00 ,  C03C2214/16 ,  C09K11/08 ,  H01L33/501 ,  H01L33/505 ,  H01L33/507

Abstract: Provided are a ternary glass composition containing SiO2, B2O3 and ZnO, and a ceramic phosphor plate including a glass frit obtained by vitrification of the glass composition as a matrix and obtained by sintering at least one phosphor.

公开(公告)号：US12167540B2

公开(公告)日：2024-12-10

申请号：US17641865

申请日：2020-09-09

Applicant: LG INNOTEK CO., LTD.

Inventor： Eui Yeol Yang ,  Se Woong Na ,  Do Hyuk Yoo

IPC: H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/28

Abstract: A printed circuit board according to an embodiment includes a first insulating layer; a first circuit pattern disposed on a lower surface or inside the first insulating layer; a second circuit pattern disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and surrounding the second circuit pattern; and a protective layer disposed on an upper surface of the second insulating layer, wherein the second insulating layer has at least one recess formed on its upper surface, and wherein the protective layer is disposed in the recess formed on the upper surface of the second insulating layer.