公开(公告)号：US20150154114A1

公开(公告)日：2015-06-04

申请号：US14169424

申请日：2014-01-31

Applicant: LSI Corporation

Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

公开(公告)号：US20140223259A1

公开(公告)日：2014-08-07

申请号：US13760609

申请日：2013-02-06

Applicant: LSI CORPORATION

Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

IPC: G06F11/10

CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.

Abstract translation: LE硬判决存储器包括用于交织来自第一和第二循环的L值的全局映射元素，并将交错值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。

公开(公告)号：US09208083B2

公开(公告)日：2015-12-08

申请号：US14169424

申请日：2014-01-31

Applicant: LSI Corporation

Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

IPC: G06F12/00 ,  G06F12/06

CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

公开(公告)号：US09037952B2

公开(公告)日：2015-05-19

申请号：US13760609

申请日：2013-02-06

Applicant: LSI Corporation

Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/27

CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

Abstract: A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.

Abstract translation: 硬判决存储器通过向多层低密度奇偶校验解码器（LDPC）发送多个L值和E值与多层低密度奇偶校验解码器相互作用，并且L值E值硬判决存储器 （LE硬决策存储器）接收一个或多个硬判决。 LE硬判决存储器包括全局映射元件，用于交织来自第一和第二循环的L值，并将交织的值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。 LE硬判决存储器的使用结果改进了LDPC编码消息的多级LDPC解码。