中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.012 seconds)

    Diversity loop detector with component detector switching
    1.
    发明授权
    Diversity loop detector with component detector switching 有权
    具有分量检测器切换的分集环路检测器

    公开(公告)号：US09407295B2

    公开(公告)日：2016-08-02

    申请号：US13741482

    申请日：2013-01-15

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Yu Kou ,  Xuebin Wu ,  Bruce A. Wilson

    IPC: G06F17/18 ,  H03M13/41

    CPC classification number: H03M13/41

    Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

    Abstract translation: 本公开的方面涉及用于为分集环路检测器提供分量检测器切换的系统和方法。 通过周期状态似然重置处理，基于斜率的切换处理或交叉连接处理之一来执行分量检测器之间的切换。 联合决策电路在组件检测器之间切换，以通过存在恒定或过渡相位偏移来促进改进的性能。

    SYSTEM AND METHOD TO INTERLEAVE MEMORY
    2.
    发明申请
    SYSTEM AND METHOD TO INTERLEAVE MEMORY 有权
    用于记忆的系统和方法

    公开(公告)号：US20150154114A1

    公开(公告)日：2015-06-04

    申请号：US14169424

    申请日：2014-01-31

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Zongwang Li ,  Shaohua Yang ,  Kaichi Zhang

    IPC: G06F12/06

    CPC classification number: G06F12/0607 ,  G11C7/1012 ,  G11C7/1042

    Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

    Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

    Memory Architecture for Layered Low-Density Parity-Check Decoder
    4.
    发明申请
    Memory Architecture for Layered Low-Density Parity-Check Decoder 有权
    分层低密度奇偶校验解码器的内存架构

    公开(公告)号：US20140223259A1

    公开(公告)日：2014-08-07

    申请号：US13760609

    申请日：2013-02-06

    Applicant: LSI CORPORATION

    Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

    IPC: G06F11/10

    CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

    Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.

    Abstract translation: LE硬判决存储器包括用于交织来自第一和第二循环的L值的全局映射元素，并将交错值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。

    Low Density Parity Check Decoder With Miscorrection Handling
    6.
    发明申请
    Low Density Parity Check Decoder With Miscorrection Handling 有权
    低密度奇偶校验解码器与误码处理

    公开(公告)号：US20140164866A1

    公开(公告)日：2014-06-12

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI CORPORATION

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/13

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 公开了一种数据处理系统，包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

    Efficient Way to Construct LDPC Code by Comparing Error Events Using a Voting Based Method
    7.
    发明申请
    Efficient Way to Construct LDPC Code by Comparing Error Events Using a Voting Based Method 有权
    通过使用基于投票的方法比较错误事件来构建LDPC码的有效方式

    公开(公告)号：US20140095955A1

    公开(公告)日：2014-04-03

    申请号：US13743381

    申请日：2013-01-17

    Applicant: LSI CORPORATION

    Inventor： Denis Vladimirovich Zaytsev ,  Denis Vasilievich Parfenov ,  Yang Han ,  Ivan Leonidovich Mazurenko ,  Dmitry Nicolaevich Babin

    IPC: H03M13/37

    CPC classification number: H03M13/3738 ,  H03M13/09 ,  H03M13/1142

    Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.

    Abstract translation: 用于排序陷阱集合以找到一个或多个主要捕获集合的方法包括分析陷阱集合和随机的码字集合以生成每个陷阱集合的距离值，并且将陷阱集合排序距离值。 可以通过跟踪投票计数来确定每个陷阱集合的距离值，其中在某一噪声级别的正确解码产生“正确”投票，并且在某一噪声电平处产生不正确的解码产生“左”投票。 一定数量的“左”选票终止在该噪声级别的处理。

    Read channel sampling utilizing two quantization modules for increased sample bit width
    9.
    发明授权
    Read channel sampling utilizing two quantization modules for increased sample bit width 有权
    使用两个量化模块读取通道采样以增加采样位宽度

    公开(公告)号：US09281007B2

    公开(公告)日：2016-03-08

    申请号：US14198008

    申请日：2014-03-05

    Applicant: LSI Corporation

    Inventor： Xuebin Wu ,  Yang Han ,  Weijun Tan ,  Shaohua Yang

    IPC: G11B20/10 ,  G11B20/14 ,  G11B5/55 ,  G11B5/012 ,  G10L19/02

    CPC classification number: G11B20/10046 ,  G10L19/0208 ,  G11B5/012 ,  G11B5/5526 ,  G11B5/553 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/1403

    Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

    Abstract translation: 公开了一种由这种通信信道结构支持的通信信道结构和解码方法。 这样的通信信道包括被配置为对输入信号进行滤波的数字滤波器和被配置为量化滤波信号的两个量化器。 利用第一量化器来量化滤波后的信号以产生具有第一精度的第一量化样本，并且使用第二量化器量化滤波信号以产生具有第二精度的第二量化样本，其中第二精度不同于 第一精度。 通信信道还包括迭代解码器，其被配置为利用第一量化样本进行解码过程的第一全局迭代，并且利用第二量化样本进行解码过程的至少一个后续全局迭代。

    Low density parity check decoder with miscorrection handling
    10.
    发明授权
    Low density parity check decoder with miscorrection handling 有权
    低密度奇偶校验解码器与错误处理

    公开(公告)号：US08996969B2

    公开(公告)日：2015-03-31

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI Corporation

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 数据处理系统包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

Patent Agency Ranking