公开(公告)号：US08996969B2

公开(公告)日：2015-03-31

申请号：US13708941

申请日：2012-12-08

Applicant: LSI Corporation

Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

Abstract translation: 数据处理系统包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

公开(公告)号：US20140281284A1

公开(公告)日：2014-09-18

申请号：US13833691

申请日：2013-03-15

Applicant: LSI Corporation

Inventor： Stefan G. Block ,  Ting Zhou ,  Mikhail I. Grinchuk ,  Anatoli A. Bolotov ,  Lav D. Ivanovic

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G11C5/04

Abstract: A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.

Abstract translation: 一种方法包括接收用于检索存储在三个存储器中的数据的多端口读取请求，每个存储器包括两个存储器模块和奇偶校验模块。 多端口读取请求与存储在第一存储器地址处的第一数据，存储在第二存储器地址的第二数据和存储在第三存储器地址的第三数据相关联。 当第一存储器地址，第二存储器地址和第三存储器地址与第一存储器模块相关联时，从第一存储器模块检索第一数据，使用来自第二存储器模块和第一奇偶校验模块的数据重建第二数据 并且使用来自第四存储器模块和第七存储器模块的数据来重建第三数据。 响应于多端口读取请求而提供第一数据，第二数据和第三数据。

公开(公告)号：US08977939B2

公开(公告)日：2015-03-10

申请号：US13723357

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Alexander S. Podkolzin ,  Shaohua Yang ,  Lav D. Ivanovic ,  Sergey Afonin

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/1142

Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

Abstract translation: 基于在低密度奇偶校验解码过程中捕获的近码字来找到有效码字的方法包括识别陷印集合配置和应用校正以产生具有有限数量的无效检查的陷印集合。 修正陷阱集合配置以便在陷阱集合表中产生陷阱集合，该表将每个校正的捕获集合与有效码字相关联。

公开(公告)号：US20140181624A1

公开(公告)日：2014-06-26

申请号：US13723357

申请日：2012-12-21

Applicant: LSI CORPORATION

Inventor： Alexander S. Podkolzin ,  Shaohua Yang ,  Lav D. Ivanovic ,  Sergey Afonin

IPC: H03M13/13

CPC classification number: H03M13/1142

Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

Abstract translation: 基于在低密度奇偶校验解码过程中捕获的近码字来找到有效码字的方法包括识别陷印集合配置和应用校正以产生具有有限数量的无效检查的陷印集合。 修正陷阱集合配置以便在陷阱集合表中产生陷阱集合，该表将每个校正的捕获集合与有效码字相关联。

公开(公告)号：US20140164866A1

公开(公告)日：2014-06-12

申请号：US13708941

申请日：2012-12-08

Applicant: LSI CORPORATION

Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

IPC: H03M13/13

CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

Abstract: A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

Abstract translation: 公开了一种数据处理系统，包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。