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    Command Barrier for a Solid State Drive Controller
    1.
    发明申请
    Command Barrier for a Solid State Drive Controller 审中-公开
    固态驱动控制器的命令屏障

    公开(公告)号：US20140331001A1

    公开(公告)日：2014-11-06

    申请号：US14268957

    申请日：2014-05-02

    Applicant: LSI Corporation

    Inventor： Yang Liu ,  Nital Patwa ,  Ming-Ju Lee ,  Yimin Chen ,  Changyou Xu ,  Tim Canepa

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods and systems may perform one or more operations for solid state device administrative command execution including, but not limited to: receiving, in at least one administrative command queue, at least one administrative command affecting at least one submission queue; halting enqueuing of one or more submission commands in the at least one submission queue in response to the receiving the at least one administrative command affecting the at least one submission queue; adding at least one barrier command to at least one submission queue affected by the at least one administrative command; processing one or more commands in the at least one submission queue until the at least one barrier command in the at least one submission queue is processed; and processing the at least one administrative command affecting the at least one submission queue in response to the processing of the at least one barrier command.

    Abstract translation: 方法和系统可以执行固态设备管理命令执行的一个或多个操作，包括但不限于：在至少一个管理命令队列中接收影响至少一个提交队列的至少一个管理命令; 响应于接收到影响至少一个提交队列的至少一个管理命令，停止在所述至少一个提交队列中排队一个或多个提交命令; 向至少一个管理命令影响的至少一个提交队列添加至少一个障碍命令; 处理所述至少一个提交队列中的一个或多个命令，直到处理所述至少一个提交队列中的所述至少一个障碍命令; 以及响应于所述至少一个障碍命令的处理，处理影响所述至少一个提交队列的所述至少一个管理命令。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    2.
    发明授权
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器

    公开(公告)号：US09166622B2

    公开(公告)日：2015-10-20

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  G06F11/10 ,  H03M13/27

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    Method to ensure data coherency in a scalable aggregate neighbor-device interface
    4.
    发明授权
    Method to ensure data coherency in a scalable aggregate neighbor-device interface 失效
    确保可扩展聚合邻居设备接口中数据一致性的方法

    公开(公告)号：US08775687B1

    公开(公告)日：2014-07-08

    申请号：US13917299

    申请日：2013-06-13

    Applicant: LSI Corporation

    Inventor： Yang Liu ,  Nital Patwa ,  Changyou Xu ,  Timothy Canepa ,  Chien Chen

    IPC: G06F3/06 ,  G06F13/12

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688

    Abstract: A method for processing a read sub-command in a secondary storage controller is disclosed. The method includes receiving the read sub-command from a primary storage controller; retrieving data in response to the read sub-command; utilizing a write request to write the retrieved data directly to a memory accessible by a host device; issuing an additional request to the same memory after the write request; receiving an indication of completion of the additional request; and reporting a sub-completion status to the primary storage controller.

    Abstract translation: 公开了一种在二次存储控制器中处理读取子命令的方法。 该方法包括从主存储控制器接收读取的子命令; 响应于读取的子命令检索数据; 利用写请求将所检索的数据直接写入由主机设备可访问的存储器; 在写请求之后向相同的存储器发出附加请求; 接收附加请求完成的指示; 并向主存储控制器报告子完成状态。

    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL
    5.
    发明申请
    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL 有权
    可编程循环低密度奇偶校验（QC LDPC）编解码器

    公开(公告)号：US20130091403A1

    公开(公告)日：2013-04-11

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/05

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

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