公开(公告)号：US09166622B2

公开(公告)日：2015-10-20

申请号：US13632768

申请日：2012-10-01

Applicant: LSI Corporation

Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  G06F11/10 ,  H03M13/27

CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

公开(公告)号：US20140229799A1

公开(公告)日：2014-08-14

申请号：US13765034

申请日：2013-02-12

Applicant: LSI CORPORATION

Inventor： Alexander Hubris ,  Hao Zhong

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/35 ,  H03M13/353 ,  H04L1/0009

Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.

Abstract translation: 一种用于在存储器中实现自适应纠错的方法，包括以下步骤：（A）解码从存储器读取的数据页面，（B）基于所解码页面的测量码字错误率来选择多个直方图中的一个 和（C）基于所选择的直方图应用纠错码率。 纠错码率允许存储器使用最小数量的纠错位来提供存储器的可靠操作。

公开(公告)号：US08898549B2

公开(公告)日：2014-11-25

申请号：US13765034

申请日：2013-02-12

Applicant: LSI Corporation

Inventor： Alexander Hubris ,  Hao Zhong

IPC: H03M13/00 ,  G06F11/10 ,  H04L1/00 ,  H03M13/35

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/35 ,  H03M13/353 ,  H04L1/0009

Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.

Abstract translation: 一种用于在存储器中实现自适应纠错的方法，包括以下步骤：（A）解码从存储器读取的数据页面，（B）基于所解码页面的测量码字错误率来选择多个直方图中的一个 和（C）基于所选择的直方图应用纠错码率。 纠错码率允许存储器使用最小数量的纠错位来提供存储器的可靠操作。

公开(公告)号：US20140104943A1

公开(公告)日：2014-04-17

申请号：US13651975

申请日：2012-10-15

Applicant: LSI CORPORATION

Inventor： Zhengang Chen ,  Hao Zhong

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

Abstract: A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

Abstract translation: 存储器件包括包括多级存储器单元的存储器阵列和耦合到存储器阵列的控制电路。 控制电路被配置为在存储器阵列的至少一部分上执行加速软读取操作。 针对存储器阵列的非上部页面的加速软读取操作中的给定的一个包括至少一个针对存储器阵列的对应的上部页面的硬读取操作。 例如，给定的加速软读取操作可以包括多个硬读操作的序列，包括针对非上页的硬读操作和针对相应上页的一个或多个硬读操作。

公开(公告)号：US20130091403A1

公开(公告)日：2013-04-11

申请号：US13632768

申请日：2012-10-01

Applicant: LSI Corporation

Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

IPC: H03M13/05

CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。