公开(公告)号：US20150195108A1

公开(公告)日：2015-07-09

申请号：US14146920

申请日：2014-01-03

Applicant: LSI Corporation

Inventor： Tomasz Prokop ,  Volodmyr Shvydun ,  Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H04L25/03 ,  H03M9/00 ,  G11C19/00

CPC classification number: H04L25/03057 ,  H03M9/00 ,  H04L2025/03535

Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Abstract translation: 一种使用串联耦合信号处理块来处理数字化输入符号的串行器 - 解串器，每个块具有系数输入。 多个串联耦合系数延迟元件中的每一个具有控制输入，并且耦合到对应的一个信号处理模块的系数输入的系数输出由具有输入和多个输出的移位寄存器控制，每个 所述多个输出耦合到所述系数延迟元件中对应的一个的所述控制输入。 适配单元具有耦合到移位寄存器的输入的标志输出，以及耦合到系数延迟元件中的第一个的输入的第一系数输出。 当自适应单元生成系数时，适配单元生成标志，并且当移位寄存器接收到标志时，该系数被输入到系数延迟元件中的第一个。

公开(公告)号：US09294313B2

公开(公告)日：2016-03-22

申请号：US14146920

申请日：2014-01-03

Applicant: LSI Corporation

Inventor： Tomasz Prokop ,  Volodmyr Shvydun ,  Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H03H7/30 ,  H03K5/159 ,  H04L25/03 ,  H03M9/00

CPC classification number: H04L25/03057 ,  H03M9/00 ,  H04L2025/03535

Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Abstract translation: 一种使用串联耦合信号处理块来处理数字化输入符号的串行器 - 解串器，每个块具有系数输入。 多个串联耦合系数延迟元件中的每一个具有控制输入，并且耦合到对应的一个信号处理模块的系数输入的系数输出由具有输入和多个输出的移位寄存器控制，每个 所述多个输出耦合到所述系数延迟元件中对应的一个的所述控制输入。 适配单元具有耦合到移位寄存器的输入的标志输出，以及耦合到系数延迟元件中的第一个的输入的第一系数输出。 当自适应单元生成系数时，适配单元生成标志，并且当移位寄存器接收到标志时，该系数被输入到系数延迟元件中的第一个。