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1.发明授权Cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权多层全图互连架构中的群集范围的系统时钟公开(公告)号：US07921316B2
公开(公告)日：2011-04-05
申请号：US11853522
申请日：2007-09-11
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
摘要： Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译： 提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的机制。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。
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2.发明授权System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权用于在多层全图互连架构中提供集群范围的系统时钟的系统公开(公告)号：US07827428B2
公开(公告)日：2010-11-02
申请号：US11848440
申请日：2007-08-31
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
CPC分类号： G06F1/12 , H04J3/0685 , H04Q2213/13092 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译： 提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。
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3.发明申请Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture 有权在多层全图互连架构中提供集群宽系统时钟的方法公开(公告)号：US20090070617A1
公开(公告)日：2009-03-12
申请号：US11853522
申请日：2007-09-11
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/12
摘要： A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译： 提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的方法。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。
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公开(公告)号：US08077602B2
公开(公告)日：2011-12-13
申请号：US12024514
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： G06F15/17
摘要： Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译： 提供了基于广播深度队列信息执行动态请求路由的机制。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。 队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。 系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。
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5.发明授权Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips 有权基于在广播心跳信号中接收到的未响应的活动源请求数量的信息进行动态路由并存储在其他处理器芯片的本地数据结构中公开(公告)号：US07779148B2
公开(公告)日：2010-08-17
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F15/163
CPC分类号： H04L45/122 , H04L45/06
摘要： A mechanism for performing dynamic request routing based on broadcast source request information is provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译： 提供了一种基于广播源请求信息进行动态请求路由的机制。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。 源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。 来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。
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6.发明申请System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information 有权基于广播源请求信息执行动态请求路由的系统和方法公开(公告)号：US20090198958A1
公开(公告)日：2009-08-06
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
CPC分类号： H04L45/122 , H04L45/06
摘要： A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译： 提供了一种基于广播源请求信息进行动态请求路由的系统和方法。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。 源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。 来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。
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7.发明申请System and Method for Performing Dynamic Request Routing Based on Broadcast Queue Depths 失效基于广播队列深度执行动态请求路由的系统和方法公开(公告)号：US20090198957A1
公开(公告)日：2009-08-06
申请号：US12024514
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
CPC分类号： G06F15/17
摘要： A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译： 提供了一种基于广播深度队列信息进行动态请求路由的系统和方法。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。 队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。 系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。
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8.发明申请System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture 有权在多层全图互连架构中提供集群宽系统时钟的系统公开(公告)号：US20090063886A1
公开(公告)日：2009-03-05
申请号：US11848440
申请日：2007-08-31
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , H04J3/0685 , H04Q2213/13092 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
摘要翻译： 提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。
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公开(公告)号：US20110173258A1
公开(公告)日：2011-07-14
申请号：US12640208
申请日：2009-12-17
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.
摘要翻译： 提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传输“集合”分组。 系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。 每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。 因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失 数据包
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公开(公告)号：US08417778B2
公开(公告)日：2013-04-09
申请号：US12640208
申请日：2009-12-17
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.
摘要翻译： 提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传送集合分组。 系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。 每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。 因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失 数据包
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