公开(公告)号：US10515815B2

公开(公告)日：2019-12-24

申请号：US15820263

申请日：2017-11-21

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Ganesh Upadhyaya ,  Yoshie Kimura ,  Weiye Zhu ,  Zhaohong Han ,  Seokhwan Lee ,  Noel Sun

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  C23C16/455 ,  H01L21/683

摘要： Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.

公开(公告)号：US20190157096A1

公开(公告)日：2019-05-23

申请号：US15820263

申请日：2017-11-21

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Ganesh Upadhyaya ,  Yoshie Kimura ,  Weiye Zhu ,  Zhaohong Han ,  Seokhwan Lee ,  Noel Sun

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  C23C16/455 ,  H01J37/32

摘要： Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.