公开(公告)号：US09515156B2

公开(公告)日：2016-12-06

申请号：US14884264

申请日：2015-10-15

申请人： Lam Research Corporation

发明人： Paul Raymond Besser ,  Bart van Schravendijk ,  Yoshie Kimura ,  Gerardo A. Delgadino ,  Harald Orkorn-Schmidt ,  Dengliang Yang

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

摘要翻译： 用于为FinFET器件提供气隙间隔件的方法包括：提供衬底多个散热片和横向于所述多个翅片设置的虚拟栅极; 在假门周围沉积牺牲隔离物; 在所述牺牲间隔物周围沉积第一层间电介质（ILD）层; 相对于第一ILD层和牺牲间隔物选择性地蚀刻虚设多晶硅栅极; 存放更换金属门（RMG）; 蚀刻RMG的一部分以产生由牺牲间隔物包围的凹部; 以及在所述凹部中沉积栅极覆盖层。 栅极覆盖层至少部分地被牺牲隔离物包围，并由碳氧化硅（SiOC）制成。

公开(公告)号：US20150053347A1

公开(公告)日：2015-02-26

申请号：US14470544

申请日：2014-08-27

申请人： Lam Research Corporation

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US20140220709A1

公开(公告)日：2014-08-07

申请号：US13758266

申请日：2013-02-04

申请人： LAM RESEARCH CORPORATION

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US11170997B2

公开(公告)日：2021-11-09

申请号：US16845746

申请日：2020-04-10

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Naveed Ansari ,  Yoshie Kimura ,  Si-Yi Yi Li ,  Kazi Sultana ,  Radhika Mani ,  Duming Zhang ,  Haseeb Kazi ,  Chen Xu ,  Mitchell Brooks ,  Ganesh Upadhyaya

IPC分类号： H01L21/02 ,  H01L21/473 ,  H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L29/78

摘要： Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.

公开(公告)号：US20210287909A1

公开(公告)日：2021-09-16

申请号：US17200526

申请日：2021-03-12

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Tom A. Kamp ,  Yoshie Kimura ,  Duming Zhang ,  Chen Xu ,  John Drewery ,  Alex Paterson

IPC分类号： H01L21/3065 ,  H01L21/67 ,  H01J37/32

摘要： A plasma processing system includes a chamber having a coil disposed above a dielectric window for providing radio frequency power to the processing region. An etch gas delivery system is coupled to gas sources used for a first etch of a material. A liquid delivery system includes a source of liquid precursor, a liquid flow controller, and a vaporizer. A controller activates the etch gas delivery system to perform the first etch and activates the liquid delivery system to perform an atomic layer passivation (ALP) process after the first etch to coat features with a conformal film of passivation. Each time the ALP process is completed a single atomic monolayer of the conformal film of passivation is formed. The controller activates the etch gas delivery system to perform a second etch, with the conformal film of passivation protecting the mask and sidewalls of the features during the second etch.

公开(公告)号：US10734238B2

公开(公告)日：2020-08-04

申请号：US15820108

申请日：2017-11-21

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Yoshie Kimura ,  Duming Zhang ,  Chen Xu ,  Ganesh Upadhyaya ,  Mitchell Brooks

IPC分类号： H01L21/3065 ,  H01L21/02 ,  C23C16/455 ,  H01L21/033 ,  H01L21/308

摘要： Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.

公开(公告)号：US10957561B2

公开(公告)日：2021-03-23

申请号：US14945680

申请日：2015-11-19

申请人： Lam Research Corporation

发明人： John Drewery ,  Yoshie Kimura ,  James Adams ,  Yoko Yamaguchi Adams ,  Tony Zemlock

IPC分类号： H01L21/67 ,  H01J37/32 ,  C23C16/455 ,  C30B25/16

摘要： A gas delivery system for a substrate processing system includes a first manifold and a second manifold. A gas delivery sub-system selectively delivers gases from gas sources. The gas delivery sub-system delivers a first gas mixture to the first manifold and a second gas mixture. A gas splitter includes an inlet in fluid communication with an outlet of the second manifold, a first outlet in fluid communication with an outlet of the first manifold, and a second outlet. The gas splitter splits the second gas mixture into a first portion at a first flow rate that is output to the first outlet and a second portion at a second flow rate that is output to the second outlet. First and second zones of the substrate processing system are in fluid communication with the first and second outlets of the gas splitter, respectively.

公开(公告)号：US10515815B2

公开(公告)日：2019-12-24

申请号：US15820263

申请日：2017-11-21

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Ganesh Upadhyaya ,  Yoshie Kimura ,  Weiye Zhu ,  Zhaohong Han ,  Seokhwan Lee ,  Noel Sun

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  C23C16/455 ,  H01L21/683

摘要： Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.

公开(公告)号：US20190043728A1

公开(公告)日：2019-02-07

申请号：US15669871

申请日：2017-08-04

申请人： Lam Research Corporation

发明人： Xiang Zhou ,  Tom A. Kamp ,  Yoshie Kimura ,  Duming Zhang ,  Chen Xu ,  John Drewery ,  Alex Paterson

IPC分类号： H01L21/3065 ,  H01L21/67 ,  H01J37/32

摘要： A method for etching a substrate includes performing, in a plasma chamber, a first etch of a substrate material using a plasma etch process. The first etch forms features to a first depth in the material. Following the first etch, the method includes performing, in the plasma chamber without removing the substrate from the chamber, an atomic layer passivation (ALP) process to deposit a conformal film of passivation over the mask and the features formed during the first etch. The ALP process uses a vapor from a liquid precursor to form passivation over the features and the mask. The method further includes performing, in the plasma chamber, a second etch of the material using the plasma etch process. The conformal film of passivation is configured to protect the mask and sidewalls of the features during the second etch. A plasma processing system also is described.

公开(公告)号：US20160111515A1

公开(公告)日：2016-04-21

申请号：US14884264

申请日：2015-10-15

申请人： Lam Research Corporation

发明人： Paul Raymond Besser ,  Bart van Schravendijk ,  Yoshie Kimura ,  Gerardo A. Delgadino ,  Harald Orkorn-Schmidt ,  Dengliang Yang

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

摘要翻译： 用于为FinFET器件提供气隙间隔件的方法包括：提供衬底多个散热片和横向于所述多个翅片设置的虚拟栅极; 在假门周围沉积牺牲隔离物; 在所述牺牲间隔物周围沉积第一层间电介质（ILD）层; 相对于第一ILD层和牺牲间隔物选择性地蚀刻虚设多晶硅栅极; 存放更换金属门（RMG）; 蚀刻RMG的一部分以产生由牺牲间隔物包围的凹部; 以及在所述凹部中沉积栅极覆盖层。 栅极覆盖层至少部分地被牺牲隔离物包围，并由碳氧化硅（SiOC）制成。