公开(公告)号：US20050009357A1

公开(公告)日：2005-01-13

申请号：US10909523

申请日：2004-08-02

申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/26506

摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

公开(公告)号：US20050086780A1

公开(公告)日：2005-04-28

申请号：US10692029

申请日：2003-10-23

申请人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

发明人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

IPC分类号： H01L27/08 ,  H01G7/00 ,  H01K3/10

CPC分类号： H01L27/0805 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49165

摘要： A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

摘要翻译： 一种形成电容器的方法，包括以下步骤。 具有形成在其上的下部低k电介质层的衬底设置有介电常数小于约3.0的下部低k电介质层。 金属垂直电极板形成在下部低k电介质层内，使得相邻的金属垂直电极板之间具有较低的低k电介质层部分。 在相邻的金属垂直电极板之间的较低的低k电介质层部分被具有大于约3.0的介电常数的高k电介质材料沟槽部分代替。