公开(公告)号：US20050086780A1

公开(公告)日：2005-04-28

申请号：US10692029

申请日：2003-10-23

申请人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

发明人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

IPC分类号： H01L27/08 ,  H01G7/00 ,  H01K3/10

CPC分类号： H01L27/0805 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49165

摘要： A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

摘要翻译： 一种形成电容器的方法，包括以下步骤。 具有形成在其上的下部低k电介质层的衬底设置有介电常数小于约3.0的下部低k电介质层。 金属垂直电极板形成在下部低k电介质层内，使得相邻的金属垂直电极板之间具有较低的低k电介质层部分。 在相邻的金属垂直电极板之间的较低的低k电介质层部分被具有大于约3.0的介电常数的高k电介质材料沟槽部分代替。

公开(公告)号：US20050009357A1

公开(公告)日：2005-01-13

申请号：US10909523

申请日：2004-08-02

申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/26506

摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

公开(公告)号：US20050059216A1

公开(公告)日：2005-03-17

申请号：US10664211

申请日：2003-09-17

申请人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

发明人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76802 ,  H01L21/76829

摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.

摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

公开(公告)号：US20060207965A1

公开(公告)日：2006-09-21

申请号：US11438188

申请日：2006-05-22

申请人： Yelehanka Ramaghandramurthy Pradeep ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zheng ,  Purakh Verma

发明人： Yelehanka Ramaghandramurthy Pradeep ,  Sanford Chu ,  Chit Hwei Ng ,  Jia Zheng ,  Purakh Verma

IPC分类号： H01B13/00

CPC分类号： H01L28/55 ,  H01L21/02109 ,  H01L21/3127 ,  H01L21/3144 ,  H01L21/31625 ,  H01L21/31629 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10T428/12035 ,  H01L2924/00

摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a a layer of choice.

摘要翻译： 一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。 具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。 这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

公开(公告)号：US20050136573A1

公开(公告)日：2005-06-23

申请号：US11045958

申请日：2005-01-28

申请人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

发明人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76802 ,  H01L21/76829

摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

公开(公告)号：US20050079658A1

公开(公告)日：2005-04-14

申请号：US10683142

申请日：2003-10-09

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/0817 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

公开(公告)号：US20050196931A1

公开(公告)日：2005-09-08

申请号：US11123748

申请日：2005-05-04

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050145953A1

公开(公告)日：2005-07-07

申请号：US10752454

申请日：2004-01-05

申请人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

发明人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L31/113

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623

摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.

摘要翻译： 一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。 提供衬底，并且在衬底上形成多晶硅层。 栅极结构和非本征基极结构形成在多晶硅层中。 多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

公开(公告)号：US20050101096A1

公开(公告)日：2005-05-12

申请号：US10703284

申请日：2003-11-06

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050116254A1

公开(公告)日：2005-06-02

申请号：US10725670

申请日：2003-12-01

申请人： Purakh Verma ,  Shao-Fu Chu ,  Lap Chan ,  Jia Zheng ,  Jian Li

发明人： Purakh Verma ,  Shao-Fu Chu ,  Lap Chan ,  Jia Zheng ,  Jian Li

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/338 ,  H01L21/8222 ,  H01L29/732 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

摘要翻译： 提供了一种用于制造异质结双极晶体管的方法。 本征收集器结构形成在衬底上。 外部基本结构部分地与本征收集器结构重叠。 内部基本结构形成在本征收集器结构附近和在非本征基础结构之下。 在本征基础结构附近形成发射极结构。 外部收集器结构形成在本征收集器结构附近。 多个触点通过层间电介质层与外部基极结构，外部基极结构和发射极结构形成。