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公开(公告)号：US07242634B2
公开(公告)日：2007-07-10
申请号：US11290205
申请日：2005-11-30
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.
摘要翻译： 在某些实施例中，本发明是用于地址解码器的字线驱动器，其解码多位地址以使得能够访问电路元件行，例如在专用存储器件中实现的存储器块中的存储器单元，或者如 更大的器件的一部分，如FPGA。 字线驱动器具有用于每个字线的反馈锁存器，以确保当该字线未被选择用于访问时字线不通电。 通过使用解码的地址位值而不是一些现有技术的动态字线驱动器的预充电使能信号控制反馈锁存器，字线驱动器防止多个字线的不期望的通电。 可以使用比一些类似的现有技术的静态字线驱动器更少的布局面积和更少的功率来实现字线驱动器。
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公开(公告)号：US06882555B2
公开(公告)日：2005-04-19
申请号：US10464083
申请日：2003-06-18
IPC分类号： G11C7/12 , G11C11/419 , G11C5/06
CPC分类号： G11C7/12 , G11C11/419
摘要： Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.
摘要翻译： 公开了用于在可编程逻辑器件上实现配置存储器的系统和方法。 例如，根据本发明的一个实施例，双向缓冲器在存储器列的部分之间实现。 缓冲器可以为延伸通过存储器列的数据线提供缓冲。
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公开(公告)号：US07535258B1
公开(公告)日：2009-05-19
申请号：US11593274
申请日：2006-11-06
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03F3/45237 , H03F3/4565 , H03F2203/45008 , H03F2203/45048 , H03F2203/45082 , H03F2203/45418 , H03F2203/45424 , H03F2203/45504 , H03F2203/45681
摘要： A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.
摘要翻译： 可编程逻辑器件的缓冲器具有可编程电流吸收和源极电路以及独立可编程的共模电压参考源。 响应于共模电压检测器和电压参考源的放大器迫使来自缓冲器的输出信号的共模电压近似来自共模电压基准源的电压。
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公开(公告)号：US07215148B1
公开(公告)日：2007-05-08
申请号：US11012548
申请日：2004-12-15
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03F3/45237 , H03F3/4565 , H03F2203/45008 , H03F2203/45048 , H03F2203/45082 , H03F2203/45418 , H03F2203/45424 , H03F2203/45504 , H03F2203/45681
摘要： A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.
摘要翻译： 用于可编程设备的缓冲器具有源电流电路，灌电流电路，一个或多个输入节点，一个或多个输出节点和开关电路。 可以可编程地控制源极电流电路以产生多个不同的总电源电流，并且可编程地控制吸收电流电路以产生多个不同的总吸收电流。 一个或多个输入节点可以接收一个或多个输入信号，并且一个或多个输出节点可呈现一个或多个输出信号。 基于一个或多个输入信号，开关电路可以选择性地将总源电流和总吸收电流中的至少一个应用于一个或多个输出节点。
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