公开(公告)号：US07242634B2

公开(公告)日：2007-07-10

申请号：US11290205

申请日：2005-11-30

Applicant: Larry R. Fenstermaker ,  Gregory S. Cartney

Inventor： Larry R. Fenstermaker ,  Gregory S. Cartney

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.

Abstract translation: 在某些实施例中，本发明是用于地址解码器的字线驱动器，其解码多位地址以使得能够访问电路元件行，例如在专用存储器件中实现的存储器块中的存储器单元，或者如 更大的器件的一部分，如FPGA。 字线驱动器具有用于每个字线的反馈锁存器，以确保当该字线未被选择用于访问时字线不通电。 通过使用解码的地址位值而不是一些现有技术的动态字线驱动器的预充电使能信号控制反馈锁存器，字线驱动器防止多个字线的不期望的通电。 可以使用比一些类似的现有技术的静态字线驱动器更少的布局面积和更少的功率来实现字线驱动器。

公开(公告)号：US07547995B1

公开(公告)日：2009-06-16

申请号：US11345713

申请日：2006-02-02

Applicant: William B. Andrews ,  Larry R Fenstermaker ,  John A. Schadt ,  Mou C. Lin

Inventor： William B. Andrews ,  Larry R Fenstermaker ,  John A. Schadt ,  Mou C. Lin

IPC: H01H9/54

CPC classification number: H03K19/00315 ,  Y10T307/944

Abstract: In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.

Abstract translation: 在本发明的一个实施例中，集成器件具有接口电路，该接口电路包括监视（至少）两个不同电源之间的相对电位的动态监视器，以使器件能够对过电压条件作出反应，从而可以进行适当的选择 为接口电路中的不同组件选择哪个电源，例如输出驱动器和输入接收器。 动态监视器可以在设备配置之前自动实现过电压保护，例如在设备通电状态期间。

公开(公告)号：US07215149B1

公开(公告)日：2007-05-08

申请号：US11012550

申请日：2004-12-15

Applicant: William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

Inventor： William B. Andrews ,  Larry R. Fenstermaker ,  John Schadt ,  Mou C. Lin

IPC: H03K19/0175

CPC classification number: H03K19/00384 ,  H03K3/356104 ,  H03K19/018521

Abstract: An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

Abstract translation: 电气系统具有主电路和接口（I / F）电路。 主电路产生主输出信号。 I / F电路接收I / F输入信号和标志信号，并产生用于应用于从电路的I / F输出信号，其中I / F输入信号基于主输出信号，并且接口电路 产生依赖于或独立于I / F输入信号的L / F输出信号，如标志信号所示。

公开(公告)号：US07129749B1

公开(公告)日：2006-10-31

申请号：US10974305

申请日：2004-10-27

Applicant: Larry R. Fenstermaker ,  John A. Schadt ,  Mou C. Lin

Inventor： Larry R. Fenstermaker ,  John A. Schadt ,  Mou C. Lin

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

Abstract: A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.

Abstract translation: 具有可编程路由结构的可编程逻辑器件（PLD），其使用诸如动态随机存取存储器（DRAM）单元的非静态存储器单元来控制可配置的电路元件，例如传输晶体管和/或MUX。 在代表性的实施例中，每个DRAM单元使用缓冲器连接到其对应的可配置电路元件，该缓冲器适于稳定由单元产生的输出电压并抵消来自单元电容器的电荷泄漏的影响。 此外，与DRAM单元相关联的刷新电路使用在后台执行的刷新操作来周期性地恢复单元电容器中的电荷，而不会干扰PLD的用户功能。 有利地，与DRAM单元相关联的相对大的电容使得本发明的PLD比依赖于SRAM单元的现有技术的PLD更不易受软错误的影响，用于其路由结构的配置控制。

公开(公告)号：US07196963B1

公开(公告)日：2007-03-27

申请号：US11251682

申请日：2005-10-17

Applicant: Larry R. Fenstermaker ,  Sajitha Wijesuriya ,  Harold N. Scholz

Inventor： Larry R. Fenstermaker ,  Sajitha Wijesuriya ,  Harold N. Scholz

IPC: G11C8/00 ,  G11C7/10

CPC classification number: G11C11/412

Abstract: In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.

Abstract translation: 在本发明的一个实施例中，一组配置存储器具有一行存储器单元，至少一行具有一组一个或多个双端口存储器单元，其适于选择性地存储配置数据或本地数据。 该行的配置地址线被分段，使得地址线经由访问控制电路连接到双端口存储器单元的配置地址端口，访问控制电路可编程地配置为阻止经由配置地址线访问那些存储器单元。 访问控制电路使得本地数据能够在正常操作期间或者从配置存储器的部分重新配置中有效且准确地存储在双端口存储单元中，而不受配置回读操作的干扰。

公开(公告)号：US07161862B1

公开(公告)日：2007-01-09

申请号：US10996283

申请日：2004-11-22

Applicant: Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

Inventor： Mou C. Lin ,  Zheng Chen ,  Larry R. Fenstermaker

IPC: G11C7/02

CPC classification number: G11C7/065

Abstract: A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.

Abstract translation: 存储读出放大器包括输出和补码输出。 读出放大器被配置为使得驱动位线低的存储单元通过使补码输出上拉而使位线锁存为低电平，并且驱动补码位线的存储单元为低电平使得能够将补码位线锁存 通过启用输出的上拉。

公开(公告)号：US5345419A

公开(公告)日：1994-09-06

申请号：US15769

申请日：1993-02-10

Applicant: Larry R. Fenstermaker ,  Kevin J. O'Connor

Inventor： Larry R. Fenstermaker ,  Kevin J. O'Connor

IPC: G06F5/14 ,  G06F5/10 ,  G11C7/00 ,  G11C8/16 ,  G11C8/00

CPC classification number: G06F5/14 ,  G11C8/16

Abstract: A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate "full" and "empty" flags, the voltage state of read and write word lines are determined in "match circuits", which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.

Abstract translation: 先进先出存储器（FIFO）包括多端口存储器阵列，其通过激活所选择的读取或写入字线来进行读取/写入操作。 读取字线由读取移位寄存器控制，写入字线由写入移位寄存器控制。 为了产生“满”和“空”标志，在“匹配电路”中确定读写字线的电压状态，比较读写指针的位置。 这消除了使用计数器，并允许移位寄存器和字线匹配电路成为单块规则结构的组成部分。 此外，它允许FIFO容易地扩展到单个字的多个字和位。

公开(公告)号：US20080143380A1

公开(公告)日：2008-06-19

申请号：US11638156

申请日：2006-12-13

Applicant: Larry R. Fenstermaker ,  Harold Scholz

Inventor： Larry R. Fenstermaker ,  Harold Scholz

IPC: H03K19/177

CPC classification number: H03K19/17792 ,  H03K19/17728

Abstract: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.

公开(公告)号：US07230810B1

公开(公告)日：2007-06-12

申请号：US11007954

申请日：2004-12-09

Applicant: William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

Inventor： William B. Andrews ,  Mou C. Lin ,  Larry R. Fenstermaker

IPC: H02H9/04

CPC classification number: H01L27/0285

Abstract: An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.

Abstract translation: 具有晶体管器件和过电压保护电路的集成电路。 晶体管器件以具有指定工作电压范围的技术实现，该晶体管器件具有栅极，漏极，源极和源极节点以及具有指定最大电压的规定工作电压范围。 过电压保护电路分别适用于门和电池的电压。 如果施加到至少一个漏极和源极节点的至少一个沟道电压超过规定的最大电压，则过电压保护电路控制栅极电压和电池电压中的至少一个以抑制一个或多个不利影响 晶体管器件。

公开(公告)号：US06975137B1

公开(公告)日：2005-12-13

申请号：US11055280

申请日：2005-02-10

Applicant: John A. Schadt ,  William B. Andrews ,  Zheng Chen ,  Anthony K. Myers ,  David A. Rhein ,  Warren L. Ziegenfus ,  Fulong Zhang ,  Ming Hui Ding ,  Larry R. Fenstermaker

Inventor： John A. Schadt ,  William B. Andrews ,  Zheng Chen ,  Anthony K. Myers ,  David A. Rhein ,  Warren L. Ziegenfus ,  Fulong Zhang ,  Ming Hui Ding ,  Larry R. Fenstermaker

IPC: H03K19/177 ,  G06F7/38 ,  G06F17/50 ,  H03K19/00

CPC classification number: H03K19/17736 ,  H03K19/17732 ,  H03K19/17796

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract translation: 具有可编程逻辑核心，块存储器和I / O电路的可编程逻辑器件（PLD）具有集成到PLD设计中的一个或多个标准单元逻辑块（SLB），以使每个SLB可编程地连接到 任何一个或多个可编程内核，块存储器和/或I / O电路。 基于标准单元的功能块的添加创建了具有增加的总体逻辑密度的PLD，相对于等效的常规PLD（例如FPGA），每个功能的净尺寸，每个功能的净模具尺寸，降低的成本以及功率和性能特性的改善。