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    MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES
    1.
    发明申请
    MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES 有权
    用于可编程逻辑器件的混合宽度存储器技术

    公开(公告)号：US20150379164A1

    公开(公告)日：2015-12-31

    申请号：US14320169

    申请日：2014-06-30

    申请人： Lattice Semiconductor Corporation

    发明人： Venkatesan Rajappan ,  Mohana Tandyala ,  Hua Xue

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054

    摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

    摘要翻译： 提供了各种技术来有效地实现可编程逻辑器件（PLD）中的用户设计。 在一个示例中，计算机实现的方法包括接收由PLD执行的操作的设计，并将该设计合成为多个PLD组件。 该合成包括在设计中检测混合模式存储器操作。 混合模式存储器操作使用具有固定数据宽度的多个嵌入式存储器块来指定具有不同读取和写入数据宽度的存储器访问。 该合成还包括确定减少数量的嵌入式存储器块以实现混合模式存储器操作，以及修改混合模式存储器操作以将存储器访问重新映射到减少数量的嵌入式存储器块。

    Mixed-width memory techniques for programmable logic devices
    3.
    发明授权
    Mixed-width memory techniques for programmable logic devices 有权
    用于可编程逻辑器件的混合宽度存储器技术

    公开(公告)号：US09576093B2

    公开(公告)日：2017-02-21

    申请号：US14320169

    申请日：2014-06-30

    申请人： Lattice Semiconductor Corporation

    发明人： Venkatesan Rajappan ,  Mohana Tandyala ,  Hua Xue

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054

    摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

    摘要翻译： 提供了各种技术来有效地实现可编程逻辑器件（PLD）中的用户设计。 在一个示例中，计算机实现的方法包括接收由PLD执行的操作的设计，并将该设计合成为多个PLD组件。 该合成包括在设计中检测混合模式存储器操作。 混合模式存储器操作使用具有固定数据宽度的多个嵌入式存储器块来指定具有不同读取和写入数据宽度的存储器访问。 该合成还包括确定减少数量的嵌入式存储器块以实现混合模式存储器操作，以及修改混合模式存储器操作以将存储器访问重新映射到减少数量的嵌入式存储器块。

    EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
    4.
    发明申请
    EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES 有权
    针对可编程逻辑器件的高效持续执行

    公开(公告)号：US20150378682A1

    公开(公告)日：2015-12-31

    申请号：US14316049

    申请日：2014-06-26

    申请人： Lattice Semiconductor Corporation

    发明人： Sunil Kumar Sharma ,  Mohana Tandyala

    IPC分类号： G06F7/575 ,  G06F5/01

    CPC分类号： G06F5/01 ,  G06F7/527 ,  G06F17/5054 ,  H03K19/17732

    摘要： Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.

    摘要翻译： 提供了各种技术来有效地实现可编程逻辑器件（PLD）中的用户设计。 在一个示例中，计算机实现的方法包括接收由PLD执行的操作的设计，并将该设计合成为多个PLD组件。 该合成包括检测设计中的常数乘法运算，确定常数乘法运算的最近边界条件，以及使用最近边界条件分解常数乘法器运算以减少多个PLD分量。 减少的多个PLD分量包括被配置为实现分解的常数乘法器操作的加法或减法运算的至少一个查询表（LUT）。