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公开(公告)号：US07735049B2
公开(公告)日：2010-06-08
申请号：US11350949
申请日：2006-02-10
IPC分类号： G06F17/50 , G01R31/3177 , G01R31/3181 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318536
摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。
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公开(公告)号：US07779322B1
公开(公告)日：2010-08-17
申请号：US11898070
申请日：2007-09-07
申请人： Zhigang Wang , Laung-Terng (L.-T.) Wang , Shianling Wu , Xiaoqing Wen , Boryau (Jack) Sheu , Zhigang Jiang
发明人： Zhigang Wang , Laung-Terng (L.-T.) Wang , Shianling Wu , Xiaoqing Wen , Boryau (Jack) Sheu , Zhigang Jiang
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.
摘要翻译： 一种在基于扫描的集成电路中压缩包含未知值的测试响应的方法和装置。 所提出的X驱动压实机包括链切换矩阵块和空间压缩逻辑块。 链路切换矩阵块在将它们馈送到空间压缩逻辑块以进行压缩之前切换内部扫描链输出，以最小化X诱导的掩蔽和错误掩蔽。 X驱动压实机还选择性地包括有限存储器压缩逻辑块，以进一步压缩空间压缩逻辑块的输出。
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公开(公告)号：US07032148B2
公开(公告)日：2006-04-18
申请号：US10876784
申请日：2004-06-28
申请人： Laung-Terng (L.-T.) Wang , Shun-Miin (Sam) Wang , Khader S. Abdel-Hafez , Xiaoqing Wen , Boryau (Jack) Sheu
发明人： Laung-Terng (L.-T.) Wang , Shun-Miin (Sam) Wang , Khader S. Abdel-Hafez , Xiaoqing Wen , Boryau (Jack) Sheu
IPC分类号： G01R31/3177 , G01R31/3181 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318536
摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。
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4.发明授权Method for performing ATPG and fault simulation in a scan-based integrated circuit 有权在基于扫描的集成电路中执行ATPG和故障模拟的方法公开(公告)号：US07210082B1
公开(公告)日：2007-04-24
申请号：US11140579
申请日：2005-05-31
申请人： Khader S. Abdel-Hafez , Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Wang , Zhigang Jiang
发明人： Khader S. Abdel-Hafez , Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Wang , Zhigang Jiang
CPC分类号： G06F11/261 , G01R31/318307 , G01R31/318547
摘要： A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703, into a Sequential Circuit Model 705. The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707. The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation 710 are performed according to the Uncontrollable/Unobservable Labeling 709 to generate the HDL Test Benches and ATE Test Programs 711.
摘要翻译： 一种在所选择的扫描测试模式或选定的自测模式中，基于所选择的捕获操作中所选择的时钟顺序，在基于扫描的集成电路中执行ATPG（自动测试模式生成）和故障模拟的方法。 该方法包括将基于输入约束702和晶圆库703的RTL（寄存器传送级）或门级HDL（硬件描述语言）代码701编译成顺序电路模型705。 然后将顺序电路模型705转换为等效的组合电路模型707，以执行前向和/或后向时钟分析708，以确定组合电路模型707中所有组合逻辑门的所有输入和输出的驱动和观察时钟。 分析结果用于组合逻辑门的所选输入和输出的不可控/不可观察标签709。 最后，ATPG和/或故障模拟710根据不可控/不可观察的标签709执行，以产生HDL测试台和ATE测试程序711。
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5.发明申请Method and apparatus for broadcasting scan patterns in a random access scan based integrated circuit 有权用于在基于随机存取扫描的集成电路中广播扫描图案的方法和装置公开(公告)号：US20060242502A1
公开(公告)日：2006-10-26
申请号：US11348519
申请日：2006-02-07
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。 所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。 在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。 消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。
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公开(公告)号：US20060064614A1
公开(公告)日：2006-03-23
申请号：US11122244
申请日：2005-05-05
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N
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7.发明授权Method and apparatus for broadcasting test patterns in a scan-based integrated circuit 有权用于在基于扫描的集成电路中广播测试模式的方法和装置公开(公告)号：US07721172B2
公开(公告)日：2010-05-18
申请号：US12216640
申请日：2008-07-09
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。 所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。 在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。 消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。
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公开(公告)号：US07590905B2
公开(公告)日：2009-09-15
申请号：US11122244
申请日：2005-05-05
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N
摘要翻译： 一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。 集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 解压缩器被嵌入在N个扫描链和M个扫描链之间，其中N
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公开(公告)号：US07231570B2
公开(公告)日：2007-06-12
申请号：US11122237
申请日：2005-05-05
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N
摘要翻译： 一种多级扫描压缩方法和装置，用于在扫描测试模式或自检模式下降低扫描链操作的速度，减少测试数据量并在基于扫描的集成电路中测试应用时间。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 将两个或更多个解压缩器嵌入在N个压缩扫描输入和M个扫描链之间，其中N
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公开(公告)号：US07945833B1
公开(公告)日：2011-05-17
申请号：US11889710
申请日：2007-08-15
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译： 一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括一个解压缩器，它包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。 解压缩器在其压缩的扫描输入端解压缩压缩的扫描图案，并将解压缩器的输出端上产生的解压缩扫描图案驱动到基于扫描的集成电路的扫描数据输入端。 由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。
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