公开(公告)号：US20050055617A1

公开(公告)日：2005-03-10

申请号：US10901298

申请日：2004-07-29

申请人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin Wang ,  Ming-Tung Chang

发明人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin Wang ,  Ming-Tung Chang

IPC分类号： G01R31/28 ,  G06F20060101 ,  H04J3/00

CPC分类号： G01R31/318594 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/318572 ,  G01R31/31905

摘要： A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division demultiplexors (TDDMs) 402, 403, decompressors 404, 405, compressors 406, 407, and time-division multiplexors (TDMs) 408, 409.

摘要翻译： 时分解复用和解压缩以选定数据速率R1 421提供的压缩输入激励421的方法和装置，以选定的数据速率R2 442驱动的解压缩的刺激424,426,433,435中，用于 在基于扫描的集成电路401中驱动所选择的扫描链。基于扫描的集成电路401包含高速时钟CK1 443，低速时钟CK2 442和多个扫描链411。 。 。 418，每个扫描链包括串联耦合的多个扫描单元。 该方法和装置包括使用多个时分解复用器（TDDM）402,403和用于将刺激421和测试响应444移入和移出高速I / O焊盘的时分复用器（TDM）408,409。 当应用于嵌入有一对或多对解压缩器404,405和压缩器406,407的基于扫描的集成电路401时，它可以进一步减少电路的测试时间，测试成本和扫描引脚数。 还提出了一种用于合成时分解复用器（TDDM）402,403，解压缩器404,405，压缩器406,407以及时分多路复用器（TDM）408,409的合成方法。

公开(公告)号：US07512851B2

公开(公告)日：2009-03-31

申请号：US10901298

申请日：2004-07-29

申请人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin (Sam) Wang ,  Ming-Tung Chang

发明人： Laung-Terng Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Fei-Sheng Hsu ,  Augusli Kifli ,  Shyh-Horng Lin ,  Shianling Wu ,  Shun-Miin (Sam) Wang ,  Ming-Tung Chang

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/318572 ,  G01R31/31905

摘要： A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.

摘要翻译： 一种方法和装置将以所选择的数据速率R1提供的压缩输入激励时分解复用和解压缩为以所选择的数据速率R2驱动的解压缩的激励，以驱动基于扫描的集成电路中的选定的扫描链，使用多个 的时分解复用器和时分复用器，用于将刺激和测试响应移入和移出高速I / O焊盘，以减少测试时间，测试成本和扫描引脚数。 还提出了一种用于合成时分复用器，解压缩器，压缩器和时分复用器的合成方法。

公开(公告)号：US20050262409A1

公开(公告)日：2005-11-24

申请号：US10850460

申请日：2004-05-21

申请人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Shun-Miin Wang

发明人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu ,  Shun-Miin Wang

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318594 ,  G01R31/3008 ,  G01R31/318342 ,  G01R31/318364 ,  G01R31/318563

摘要： A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.

摘要翻译： 一种用于产生用于以选定的扫描测试模式或选定的自测模式测试基于扫描的集成电路中的故障的刺激和测试响应的方法，所述基于扫描的集成电路包含多个扫描链，N个时钟域， 和C个跨时钟域块，每个扫描链包括串联耦合的多个扫描单元，每个时钟域具有一个捕获时钟，每个交叉时钟域块包括组合逻辑网络。 该方法包括将基于扫描的集成电路编译成顺序电路模型; 在移位和捕获操作期间指定基于扫描的集成电路的输入约束; 指定时钟分组以将N个时钟域映射到G个时钟域组，其中N> G> 1; 根据输入约束和时钟分组将顺序电路模型转换为等效组合电路模型; 并根据输入约束在等效组合电路模型上产生刺激和测试响应。

公开(公告)号：US20050060625A1

公开(公告)日：2005-03-17

申请号：US10876784

申请日：2004-06-28

申请人： Laung-Terng Wang ,  Shun-Miin Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu

发明人： Laung-Terng Wang ,  Shun-Miin Wang ,  Khader Abdel-Hafez ,  Xiaoqing Wen ,  Boryau Sheu

IPC分类号： G01R31/28 ,  H01L20060101

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US06957403B2

公开(公告)日：2005-10-18

申请号：US10108238

申请日：2002-03-28

申请人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

发明人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

公开(公告)号：US20050268194A1

公开(公告)日：2005-12-01

申请号：US11122237

申请日：2005-05-05

申请人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Boryau Sheu ,  Shianling Wu

发明人： Laung-Terng Wang ,  Khader Abdel-Hafez ,  Boryau Sheu ,  Shianling Wu

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318547

摘要： A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus comprises two or more decompressors embedded between N compressed scan inputs and M scan chains, where N

摘要翻译： 一种多级扫描压缩方法和装置，用于在扫描测试模式或自检模式下降低扫描链操作的速度，减少测试数据量并在基于扫描的集成电路中测试应用时间。 基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。 该方法和装置包括嵌入在N个压缩扫描输入和M个扫描链之间的两个或更多个解压缩器，其中N

公开(公告)号：US20090037786A1

公开(公告)日：2009-02-05

申请号：US12285225

申请日：2008-09-30

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US20060156122A1

公开(公告)日：2006-07-13

申请号：US11350949

申请日：2006-02-10

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Boryau Sheu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Boryau Sheu

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US07412672B1

公开(公告)日：2008-08-12

申请号：US11104651

申请日：2005-04-13

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

IPC分类号： G06F17/50

CPC分类号： G01R31/3177 ,  G01R31/318533 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.

公开(公告)号：US20090235132A1

公开(公告)日：2009-09-17

申请号：US12468909

申请日：2009-05-20

申请人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547 ,  G01R31/318591

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。