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公开(公告)号：US20220358071A1
公开(公告)日：2022-11-10
申请号：US17737415
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Chuang ZHANG , Junmou ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/40
Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
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公开(公告)号：US20240345620A1
公开(公告)日：2024-10-17
申请号：US18634421
申请日：2024-04-12
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Weifeng DONG , Jincai YE , Yuanlin CHENG , Pengfei LIU , Xinxia JIA , Shan LU , Jian WANG
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A chip, a chip system, and a timestamp synchronization method. The chip is configured to be in communication connection to another chip, and includes a signal generating module, a first signal response module and a first delay module. The signal generating module is configured to generate a synchronization request signal and transmit the synchronization request signal to the first signal response module and the another chip, so that the another chip records a second timestamp of the another chip in response to receiving the synchronization request signal. The first delay module is configured to perform delay processing on the synchronization request signal to obtain a delayed synchronization request signal. The first signal response module is configured to record a first timestamp of the chip in response to receiving the delayed synchronization request signal, wherein the first timestamp and the second timestamp are used for performing a timestamp synchronization operation.
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公开(公告)号：US20240152474A1
公开(公告)日：2024-05-09
申请号：US18414920
申请日：2024-01-17
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Chuang ZHANG , Junmou ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/40
CPC classification number: G06F13/4027 , G06F2213/40
Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
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公开(公告)号：US20220358078A1
公开(公告)日：2022-11-10
申请号：US17737527
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Yimin CHEN , Shan LU , Junmou ZHANG , Chuang ZHANG , Yuanlin CHENG , Jian WANG
IPC: G06F13/42 , G06F13/40 , G06F15/173 , G06F9/30
Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.
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Patent Agency Ranking
公开(公告)号：US20220357215A1
公开(公告)日：2022-11-10
申请号：US17736157
申请日：2022-05-04
Applicant: Lemon Inc.
Inventor： Chuang ZHANG , Shan LU , Junmou ZHANG , Yimin CHEN , Jian WANG , Yuanlin CHENG
Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.
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公开(公告)号：US20240168516A1
公开(公告)日：2024-05-23
申请号：US18513433
申请日：2023-11-17
Applicant: Beijing Youzhuju Network Technology Co., Ltd. , Lemon Inc.
Inventor： Jincai YE , Yuanlin CHENG , Shan LU , Jian WANG
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A clock synchronization method and apparatus, an electronic device and a storage medium are provided. The clock synchronization method includes: sending a trigger signal to a second processing module and recording a current count value of the first timer upon sending the trigger signal as a first count value; and reading a second count value from the second processing module, the second count value is a current count value of a second timer of the second processing module upon the second processing module receiving the trigger signal, and a count value of the second timer is used as a timing reference of the second processing module and sequentially increasing; the first count value and the second count value are used for a clock compensation to synchronize a first clock domain where the first processing module is located with a second clock domain where the second processing module is located.
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公开(公告)号：US20220358184A1
公开(公告)日：2022-11-10
申请号：US17736131
申请日：2022-05-04
Applicant: Lemon Inc.
Inventor： Chuang ZHANG , Shan LU , Junmou ZHANG , Yimin CHEN , Jian WANG , Yuanlin CHENG
Abstract: A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.
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公开(公告)号：US20220357924A1
公开(公告)日：2022-11-10
申请号：US17737327
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Chuang ZHANG , Shan LU , Junmou ZHANG , Yimin CHEN , Yuanlin CHENG , Jian WANG
Abstract: A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.
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公开(公告)号：US20220357370A1
公开(公告)日：2022-11-10
申请号：US17737373
申请日：2022-05-05
Applicant: Lemon Inc.
Inventor： Junmou ZHANG , Shan LU , Chuang ZHANG , Yimin CHEN , Jian WANG , Yuanlin CHENG
IPC: G01R19/10 , H03K17/687
Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.
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